CN-121997853-A - Digital circuit design method, device, equipment and medium

CN121997853ACN 121997853 ACN121997853 ACN 121997853ACN-121997853-A

Abstract

The invention discloses a digital circuit design method, a device, equipment and a medium, which relate to the technical field of digital circuits and comprise the steps of determining a target type of a digital circuit to be designed, collecting a first training set corresponding to the target type, wherein each training sample in the first training set comprises an input characteristic item of a historical digital circuit for designing the target type and actual result quality of the historical digital circuit, the input characteristic item comprises a high-level language source code and HLS constraint parameters, constructing an initial prediction model based on a multi-layer perceptron hybrid structure, training the initial prediction model by using the first training set, searching an optimized model framework based on a network structure to obtain a target prediction model, predicting the actual result quality corresponding to each parameter combination in a target design space of the digital circuit to be designed by using the model, and designing the digital circuit by using the parameter combination with the quality meeting the pareto front. And predicting accurate actual quality results by using a prediction model without intermediate representation so as to carry out digital circuit design.

Inventors

LI GUOQING
LI RENGANG
LI TUO
WANG CHANGHONG
CHEN TINGHUAN

Assignees

山东云海国创云计算装备产业创新中心有限公司

Dates

Publication Date: 20260508
Application Date: 20260128

Claims (10)

1. A digital circuit design method, comprising: Determining a target type of a digital circuit to be designed, and collecting a first training set corresponding to the target type, wherein each training sample in the first training set comprises an input characteristic item for designing a historical digital circuit of the target type and actual result quality of the historical digital circuit, and the input characteristic item comprises a high-level language source code and a high-level comprehensive constraint parameter; Constructing an initial prediction model based on a multi-layer perceptron hybrid structure, training the initial prediction model by using the first training set, and searching and optimizing a model framework of the initial prediction model based on a network structure to obtain a target prediction model; and determining each high-level comprehensive constraint parameter combination in the target design space of the digital circuit to be designed as each sampling point, predicting the actual result quality corresponding to each sampling point by using the target prediction model, determining the sampling point with the actual result quality meeting the pareto front as a target sampling point, and designing the digital circuit by using the target high-level comprehensive constraint parameter combination corresponding to the target sampling point.
2. The digital circuit design method according to claim 1, wherein the acquiring the first training set corresponding to the target type comprises: Collecting a plurality of groups of input characteristic items corresponding to the target types and the actual result quality of a digital circuit designed by utilizing each input characteristic item so as to construct a plurality of original training samples; And performing data cleaning and standardization processing on the original training samples to construct a first training set corresponding to the target type by using the final training samples.
3. The digital circuit design method according to claim 1, wherein before the acquiring the first training set corresponding to the target type, further comprising: Writing high-level language source codes for designing the target type historical digital circuit by using any one or more high-level languages of a C language, a C++ language and a SystemC language, and modifying initial high-level comprehensive constraint parameters corresponding to the historical digital circuit for multiple times to obtain a plurality of groups of input characteristic items containing the high-level language source codes and the high-level comprehensive constraint parameters; And converting each group of input characteristic items into a register transmission level description code of the historical digital circuit, physically realizing the register transmission level description code, then burning the register transmission level description code in a field programmable logic gate array to obtain the historical digital circuit, and carrying out quality assessment on the historical digital circuit to obtain the actual result quality comprising the performance, the power consumption and the area of the historical digital circuit.
4. The digital circuit design method of claim 1, wherein the initial predictive model comprises a normalization layer, a blending layer, a global averaging pooling layer, and a regression head, wherein the blending layer comprises a set of blended multi-layer perceptrons and a channel blended multi-layer perceptrons, wherein training the initial predictive model using the first training set comprises: inputting each of the training samples in the first training set into the initial predictive model; The method comprises the steps that dimension differences of all features in an input training sample are eliminated through a normalization layer, normalized features are output, the normalized features are subjected to cross-group feature aggregation by a group mixed multi-layer perceptron, aggregated features are output, single feature mining is performed on the aggregated features by a channel mixed multi-layer perceptron, a feature matrix is output, feature dimension reduction is performed on the feature matrix by a global average pooling layer, dimension reduction features are output, and regression maps the dimension reduction features to predicted actual result quality.
5. The method of claim 4, wherein the super parameters to be adjusted of the initial predictive model include a hidden layer size and an output layer size of the set of hybrid multi-layer perceptron, a hidden layer size and an output layer size of the channel hybrid multi-layer perceptron, and a total number of stacked layers of the hybrid layers, wherein the network structure-based search optimizes a model architecture of the initial predictive model to obtain a target predictive model, comprising: According to the scale of the first training set, self-adapting the search space of the super parameter to be adjusted; and performing iterative search on the hyper-parameter combinations in the search space by taking a reinforcement learning algorithm as a search strategy and the prediction accuracy of the initial prediction model as a reward function until a preset stopping condition is met, so as to determine a target model architecture, and acquiring a target prediction model based on the target model architecture.
6. The digital circuit design method according to any one of claims 1 to 5, wherein the determining each high-level comprehensive constraint parameter combination in the target design space of the digital circuit to be designed as each sampling point includes: Setting boundary requirements of the actual result quality predicted by the target prediction model, wherein the boundary requirements comprise a lower performance limit, an upper power consumption limit and an area threshold of the digital circuit to be designed; setting a target design space of the digital circuit to be designed based on the boundary requirement; And determining each high-level comprehensive constraint parameter combination in the target design space as each sampling point, wherein the high-level comprehensive constraint parameter combination comprises pipeline depth, cycle expansion times, storage bandwidth and resource constraint of the digital circuit to be designed.
7. The digital circuit design method according to claim 6, wherein predicting the actual result quality corresponding to each of the sampling points using the target prediction model, and determining the sampling point for which the actual result quality satisfies the pareto front as the target sampling point, comprises: randomly selecting part of current sampling points from the target design space, outputting predicted values of actual result quality corresponding to the current sampling points by utilizing the target prediction model, and integrating the current sampling points and the corresponding predicted values to construct a current sampling set; Constructing a multi-target current Gaussian process proxy model taking the current sampling set as a second training set, wherein a fitting component of the current Gaussian process proxy model comprises a multi-target optimized kernel function; Inputting the current sampling set into the current Gaussian process proxy model so that the current Gaussian process proxy model generates a prediction mean and a prediction variance of a predicted value according to a nonlinear mapping relation between each sampling point in the current sampling set and the corresponding predicted value; Setting a multi-target acquisition function, inputting the prediction mean value and the prediction variance into the multi-target acquisition function, and determining a new current sampling point in the target design space by solving the maximum value of the multi-target acquisition function; outputting a predicted value of the actual result quality corresponding to the new current sampling point by using the target prediction model, and adding the new current sampling point and the corresponding predicted value to the current sampling set to obtain a new current sampling set; Re-jumping to the step of inputting the current sampling set into the current Gaussian process proxy model until a preset iteration stop condition is met, so as to obtain a final sampling set; And carrying out pareto optimal solution screening on all sampling points in the final sampling set and the predicted value of the corresponding actual result quality based on a non-dominant ordering rule of multi-objective optimization, and determining the sampling points in the pareto optimal solution set obtained by screening as target sampling points meeting the pareto front edge.
8. A digital circuit design apparatus, comprising: The training set determining module is used for determining the target type of the digital circuit to be designed and collecting a first training set corresponding to the target type, wherein each training sample in the first training set comprises an input characteristic item of a historical digital circuit for designing the target type and the actual result quality of the historical digital circuit, and the input characteristic item comprises a high-level language source code and a high-level comprehensive constraint parameter; The prediction model acquisition module is used for constructing an initial prediction model based on the multi-layer perceptron hybrid structure, training the initial prediction model by utilizing the first training set, and searching and optimizing a model framework of the initial prediction model based on a network structure so as to obtain a target prediction model; And the digital circuit design module is used for determining each high-level comprehensive constraint parameter combination in the target design space of the digital circuit to be designed as each sampling point, predicting the actual result quality corresponding to each sampling point by utilizing the target prediction model, determining the sampling point with the actual result quality meeting the pareto front as the target sampling point, and designing the digital circuit by utilizing the target high-level comprehensive constraint parameter combination corresponding to the target sampling point.
9. An electronic device, comprising: A memory for storing a computer program; A processor for executing the computer program to implement the steps of the digital circuit design method as claimed in any one of claims 1 to 7.
10. A computer-readable storage medium storing a computer program, wherein the computer program when executed by a processor implements the steps of the digital circuit design method according to any one of claims 1 to 7.

Description

Digital circuit design method, device, equipment and medium Technical Field The present invention relates to the field of digital circuits, and in particular, to a digital circuit design method, apparatus, device, and medium. Background In the field of digital circuit design, a High-LEVEL SYNTHESIS (HLS) technology becomes a core means for connecting a High-level language with hardware implementation, and by the technology, a High-level language source code can be converted into a register transmission level description code, so that the rapid design of a digital circuit is realized, the actual result quality is used as a core index for measuring the design effect of the digital circuit, and how to realize multi-objective optimization of the actual result quality of the digital circuit by optimizing High-level comprehensive constraint parameters is a core requirement of the current digital circuit design. In the traditional digital circuit design process, high-level comprehensive constraint parameters are manually adjusted by depending on experience of engineers, and actual effects of flow verification parameter combination are achieved through multiple times of physics, so that a large amount of time and labor cost are needed to be input, the trial-and-error period is long, and optimal balance is difficult to achieve in multiple target dimensions of performance, power consumption and area. Design parameter screening is assisted by a predictive model, but such models often employ conventional network structures, which generally cannot directly take design points as inputs, rather, they require extracting intermediate representations (INTERMEDIATE REPRESENTATION, i.e., IR) from HLS tools and generating control dataflow graphs using graph constructors as inputs to the model, which makes the process cumbersome, ultimately leading to low digital circuit design efficiency and high design costs. In summary, how to predict accurate actual quality results using a predictive model that does not require intermediate representation for digital circuit design is a problem to be solved in the art. Disclosure of Invention In view of the above, an object of the present invention is to provide a digital circuit design method, apparatus, device, and medium for predicting accurate actual quality results using a prediction model that does not require intermediate representation, so as to perform digital circuit design. The specific scheme is as follows: in a first aspect, the present invention discloses a digital circuit design method, comprising: Determining a target type of a digital circuit to be designed, and collecting a first training set corresponding to the target type, wherein each training sample in the first training set comprises an input characteristic item for designing a historical digital circuit of the target type and actual result quality of the historical digital circuit, and the input characteristic item comprises a high-level language source code and a high-level comprehensive constraint parameter; Constructing an initial prediction model based on a multi-layer perceptron hybrid structure, training the initial prediction model by using the first training set, and searching and optimizing a model framework of the initial prediction model based on a network structure to obtain a target prediction model; and determining each high-level comprehensive constraint parameter combination in the target design space of the digital circuit to be designed as each sampling point, predicting the actual result quality corresponding to each sampling point by using the target prediction model, determining the sampling point with the actual result quality meeting the pareto front as a target sampling point, and designing the digital circuit by using the target high-level comprehensive constraint parameter combination corresponding to the target sampling point. Optionally, the acquiring a first training set corresponding to the target type includes: Collecting a plurality of groups of input characteristic items corresponding to the target types and the actual result quality of a digital circuit designed by utilizing each input characteristic item so as to construct a plurality of original training samples; And performing data cleaning and standardization processing on the original training samples to construct a first training set corresponding to the target type by using the final training samples. Optionally, before the acquiring the first training set corresponding to the target type, the method further includes: Writing high-level language source codes for designing the target type historical digital circuit by using any one or more high-level languages of a C language, a C++ language and a SystemC language, and modifying initial high-level comprehensive constraint parameters corresponding to the historical digital circuit for multiple times to obtain a plurality of groups of input characteristic items containing the hig