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CN-121997855-A - UART digital logic simulation architecture system based on Verilog HDL

CN121997855ACN 121997855 ACN121997855 ACN 121997855ACN-121997855-A

Abstract

The invention discloses a UART digital logic simulation architecture system based on Verilog HDL, which comprises a demand module, a test case TESTCASE module, a command model CMD_MOD module and an asynchronous serial port model UART_MOD module, wherein the UART digital logic simulation architecture based on Verilog HDL is established, the problems that the application scene of the existing UART simulation architecture is single and needs to be continuously modified to be suitable for various application scenes of various projects are solved, and the simulation verification efficiency of various application scenes of various projects about UART is improved by parameter transmission and analysis.

Inventors

  • HUANG HANLING

Assignees

  • 北京轩宇信息技术有限公司

Dates

Publication Date
20260508
Application Date
20251208

Claims (7)

  1. 1. A UART digital logic simulation architecture system based on Verilog HDL is characterized by comprising a demand module, a test case TESTCASE module, a command model CMD_MOD module and an asynchronous serial port model UART_MOD module; The demand module is used for providing frame protocol, UART protocol and case demands; The test case TESTCASE module is used for setting instruction data according to frame protocol requirements, setting parameters according to case requirements, calling the instruction model CMD_MOD module, and transmitting the instruction data and the parameters to the instruction model CMD_MOD module; The command model CMD_MOD module is used for analyzing command data, byte setting parameters and UART protocol requirements, determining byte data meeting the requirements, failing to meet error bit positions of the UART protocol, calling the asynchronous serial port model UART_MOD module and transmitting related parameters; The UART_MOD module of the asynchronous serial port model is used for analyzing bytes to be sent and bit setting parameters, and sending bit data meeting requirements according to UART protocol requirements.
  2. 2. The UART digital logic simulation architecture system based on Verilog HDL according to claim 1, wherein the test case TESTCASE module comprises an instruction data setting unit and a parameter setting unit; the instruction data setting unit is used for setting a frame length and an instruction data array according to the frame protocol requirement, wherein the frame length and the bit width are 16 bits, the content is the whole frame byte number, the array capacity is 1024 16 bits, and the set instruction data is allowed to be not more than 1024 bytes; The parameter setting unit is used for setting byte setting parameters and bit setting parameters, wherein the byte setting parameters comprise frame check setting and error bit setting, and the bit setting parameters comprise byte check bit setting, idle bit setting, 8-bit data transmission sequence setting, baud rate setting and baud rate deviation setting.
  3. 3. The UART digital logic simulation architecture system based on Verilog HDL according to claim 2, wherein the frame check settings include a frame check type, a frame check start and stop byte sequence number, and a frame check field high and low byte sequence number, the error bit settings include an error bit byte sequence number and a bit sequence number, the byte check bit settings include a byte check type and a byte check bit sequence number, and the idle bit settings include an idle bit number.
  4. 4. The UART digital logic simulation architecture system based on Verilog HDL of claim 1, wherein the command model CMD_MOD module includes a byte setting unit and a send byte unit; The byte setting unit is used for analyzing the 32-bit frame check setting parameter TCHK and the 32-bit error bit position setting parameter NOERR, and determining the byte sequence number and the bit sequence number of the frame check related information and the error bit which does not meet the frame protocol; The byte sending unit is used for analyzing the frame length LEN and the frame data WORD 0-1023, determining the specific content of byte data to be sent by combining the frame check field value, the error byte and the error bit information, and transmitting the bytes to be sent to the UART_MOD module of the asynchronous serial port model.
  5. 5. The UART digital logic simulation architecture system based on Verilog HDL according to claim 4, wherein the high 8 bits of the 32-bit frame check setting parameter TCHK are frame check type setting parameters, bits [23:16], [15:8] are frame check start and stop byte sequence numbers, bits [7:4], [3:0] are frame check field high and low byte sequence numbers, and the high 16 bits of the 32-bit error bit position setting parameter NOERR are error bit byte sequence numbers, and the low 16 bits are error bit sequence numbers.
  6. 6. The UART digital logic simulation architecture system based on Verilog HDL of claim 1, wherein the asynchronous serial port model UART_MOD module comprises a bit setting unit and a sending bit unit; the bit setting unit is used for analyzing UART protocol, 32 bit byte check and idle bit setting parameter PARITY, 32 bit baud rate setting parameter RBAUD and baud rate deviation setting parameter SPEED, and determining byte check related information, idle bit number, 8 bit data transmission sequence and bit transmission rate; the sending bit unit is used for receiving bytes to be sent, determining the bit sequence sent by each byte according to the information obtained by bit setting analysis, and sending bit data according to the bit sequence.
  7. 7. The UART digital logic simulation architecture system based on Verilog HDL according to claim 6, wherein the high 8 bits of the 32 bit byte check and idle bit setting parameter PARITY are byte check type setting, bits [23:16] are byte check bit sequence number setting, bits [15:8] are idle bit number setting, bits [7:0] are 8 bit data transmission sequence setting, and the bit transmission rate is calculated according to the 32 bit baud rate setting parameter RBAUD and the baud rate deviation setting parameter SPEED.

Description

UART digital logic simulation architecture system based on Verilog HDL Technical Field The invention relates to the technical field of simulation test, in particular to a UART digital logic simulation architecture system based on Verilog HDL. Background Simulation verification is an essential step of digital logic design test, and is one of effective means for guaranteeing digital logic design quality. The quality of the input data for testing directly influences the testing effect, and numerous application scenes such as UART functions, performance, interface protocols and the like are comprehensively evaluated, and the input data is required to have personalized characteristics. In the function test, the instruction types in all interface protocols are required to be covered to confirm that all input UART data can be correctly received, analyzed and executed, the baud rate of the input data is required to be changed to search the baud rate boundary in the performance test, and the specified bits or fields are required to violate the protocol in the interface protocol test to verify whether abnormal input data can be correctly processed without influencing the receiving, analyzing and executing of subsequent UART data. Meanwhile, the difficulty degree of the input data for testing directly influences the testing efficiency. The testing period is mainly distributed in three stages of design understanding before testing, environment construction in testing and data recording and arrangement after testing, and the most intuitive mode for evaluating the friendly degree of the simulation framework is based on the difficulty degree generated by input data for testing. The existing UART simulation architecture has the problem of single application scene, various application scenes of each project can be adapted only by continuous modification, the testing workload is increased, the testing period is prolonged, and the requirement that the current testing period is continuously compressed cannot be met. Therefore, a UART digital logic simulation architecture that can adapt to various application scenarios, simplify the input data generation process for testing, and improve the simulation verification efficiency is needed. Disclosure of Invention The invention aims to provide a UART digital logic simulation architecture system based on Verilog HDL, which solves the problems existing in the prior art. In order to achieve the purpose, the invention provides a UART digital logic simulation architecture system based on Verilog HDL, which comprises a demand module, a test case TESTCASE module, a command model CMD_MOD module and an asynchronous serial port model UART_MOD module; The demand module is used for providing frame protocol, UART protocol and case demands; The test case TESTCASE module is used for setting instruction data according to frame protocol requirements, setting parameters according to case requirements, calling the instruction model CMD_MOD module, and transmitting the instruction data and the parameters to the instruction model CMD_MOD module; The command model CMD_MOD module is used for analyzing command data, byte setting parameters and UART protocol requirements, determining byte data meeting the requirements, failing to meet error bit positions of the UART protocol, calling the asynchronous serial port model UART_MOD module and transmitting related parameters; The UART_MOD module of the asynchronous serial port model is used for analyzing bytes to be sent and bit setting parameters, and sending bit data meeting requirements according to UART protocol requirements. Preferably, the test case TESTCASE module includes an instruction data setting unit and a parameter setting unit; the instruction data setting unit is used for setting a frame length and an instruction data array according to the frame protocol requirement, wherein the frame length and the bit width are 16 bits, the content is the whole frame byte number, the array capacity is 1024 16 bits, and the set instruction data is allowed to be not more than 1024 bytes; The parameter setting unit is used for setting byte setting parameters and bit setting parameters, wherein the byte setting parameters comprise frame check setting and error bit setting, and the bit setting parameters comprise byte check bit setting, idle bit setting, 8-bit data transmission sequence setting, baud rate setting and baud rate deviation setting. Preferably, the frame check setting comprises a frame check type, a frame check start-stop byte sequence number and a frame check field high-low byte sequence number, the error bit setting comprises an error bit byte sequence number and a bit sequence number, the byte check bit setting comprises a byte check type and a byte check bit sequence number, and the idle bit setting comprises the number of idle bits. Preferably, the command model cmd_mod module includes a byte setting unit and a byte sending unit; The byte setting un