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CN-121997856-A - Large-scale SoC test method and device based on multi-FPGA chip cascading

CN121997856ACN 121997856 ACN121997856 ACN 121997856ACN-121997856-A

Abstract

The invention relates to the technical field of SoC test, in particular to a large-scale SoC test method and device based on multi-FPGA chip cascading. The method comprises the steps of evaluating the resource occupancy rate of each module on the SoC, mapping each module onto a plurality of FPGA chips according to the resource occupancy rate of each module, connecting two adjacent FPGA chips in series in sequence to conduct data communication of the two adjacent FPGA chips so as to realize cascading of all the FPGA chips, respectively carrying out comprehensive and implementation processing on each FPGA design to generate a bit stream file, burning the bit stream file into each FPGA chip, and after all the FPGA chips are reset according to a correct time sequence, carrying out SoC function test on all the FPGA chips as a whole. The invention can get rid of the problem of resource limitation of a single FPGA chip, so as to realize the function test of a complete large-scale SoC system by utilizing a plurality of cascaded FPGA chips.

Inventors

  • ZHANG WUJI

Assignees

  • 芯动微电子科技(北京)有限公司

Dates

Publication Date
20260508
Application Date
20251225

Claims (10)

  1. 1. A large scale SoC test method based on multi-FPGA chip cascade is characterized in that the large scale SoC comprises a plurality of modules, comprising: Evaluating the resource occupancy rate of each module on the SoC; According to the resource occupancy rate of each module, mapping each module onto a plurality of FPGA chips respectively; connecting two adjacent FPGA chips in series in sequence to perform data communication of the two adjacent FPGA chips, so as to realize cascade connection of all the FPGA chips; respectively carrying out synthesis and implementation processing on each FPGA design, generating a bit stream file, and burning the bit stream file to each FPGA chip; after all the FPGA chips are reset according to the correct time sequence, all the FPGA chips are used as a whole for SoC function test.
  2. 2. The method for testing the large SoC based on the cascade connection of the plurality of FPGA chips as claimed in claim 1, wherein the mapping each module onto the plurality of FPGA chips according to the resource occupancy rate of each module includes: Acquiring the resource occupancy rate of each module; And determining the mapped FPGA chips according to the resource occupancy rate of each module in sequence from high to low so as to map each module onto a plurality of FPGA chips, wherein each FPGA chip comprises one or more modules, and the sum of the resource occupancy rates of all the modules on the FPGA chip is smaller than or equal to the resource threshold value of the FPGA chip.
  3. 3. The large SoC test method based on multi-FPGA chip cascading of claim 2, wherein the two adjacent FPGA chips are sequentially connected in series to perform data communication of the two adjacent FPGA chips, so as to implement cascading of all FPGA chips, including: For an FPGA chip, the FPGA chip comprises an internal module and an IP core, wherein serial data generated by the module is transmitted to the IP core through an on-chip bus; Converting the parallel data into serial data through a transceiver, and leading out the serial data through an I/O pin and an external expansion interface of the FPGA chip; transmitting the serial data led out from the external expansion interface to another FPGA chip adjacent to the FPGA chip through a high-speed serial link to obtain a data path of two adjacent FPGA chips; And connecting two adjacent FPGA chips in sequence according to the data path so as to realize cascade connection of all the FPGA chips.
  4. 4. The large SoC testing method based on multi-FPGA chip cascading of claim 3, wherein the on-chip bus includes a first on-chip bus and a second on-chip bus, the method further comprising: Determining bus protocol types of modules in two adjacent FPGA chips for data interaction; for an FPGA chip, judging whether a protocol conversion module needs to be added between a module and an IP core according to the bus protocol type; If a protocol conversion module needs to be added, connecting the module with the protocol conversion module through a second on-chip bus, and connecting the protocol conversion module with the IP core through a first on-chip bus; And if the protocol conversion module is not required to be added, connecting the module with the IP core through a first on-chip bus.
  5. 5. The large-scale SoC test method based on multi-FPGA chip cascading of claim 1, wherein after all FPGA chips are reset according to a correct timing sequence, performing SoC function test on all FPGA chips as a whole, including: According to the data flow direction between two adjacent FPGA chips, configuring the two adjacent FPGA chips into a master FPGA chip and a slave FPGA chip respectively, wherein an IP core in the master FPGA chip is a master IP core, and an IP core in the slave FPGA chip is a slave IP core; And controlling a second global reset signal of the main IP core through the first global reset signal of the auxiliary IP core so as to enable the IP cores in two adjacent FPGA chips to be reset according to a correct time sequence, and performing SoC function test on all the FPGA chips as a whole after the IP cores in all the FPGA chips are reset according to the correct time sequence.
  6. 6. The large SoC testing method based on multi-FPGA chip cascading of claim 5, further comprising: the slave IP core receives a first global reset signal, wherein when the first global reset signal is at a high level, the slave IP core releases reset, and when the first global reset signal is at a low level, the slave IP core maintains a reset state; transmitting the first global reset signal to a main IP core, and carrying out phase-adding on the first global reset signal and a local reset signal of the main IP core to obtain a second global reset signal, wherein the main IP core is reset when the second global reset signal is at a high level, and the main IP core is kept in a reset state when the second global reset signal is at a low level.
  7. 7. The large SoC testing method based on multi-FPGA chip cascading of claim 6, further comprising: When the bit stream file is burnt to a main FPGA chip, setting a local reset signal of the main IP core to be high level; Acquiring the first global reset signal transmitted from the IP core, and phase-separating the first global reset signal and the local reset signal to obtain a second global reset signal of the main IP core, wherein the first global reset signal is in a low level, and the second global reset signal is in a low level; When the bit stream file is burnt to a slave FPGA chip, setting a first global reset signal of the slave IP core from a low level to a high level; And transmitting the high level to the main IP core, and carrying out phase-locking with the local reset signal to obtain a second global reset signal of the main IP core, wherein the second global reset signal is high level.
  8. 8. The large SoC test method based on multi-FPGA chip cascading of claim 5, wherein the configuring the two adjacent FPGA chips as the master FPGA chip and the slave FPGA chip according to the data flow direction between the two adjacent FPGA chips includes: taking the FPGA chip at the data transmitting end as a master FPGA chip and taking the FPGA chip at the data receiving end as a slave FPGA chip.
  9. 9. The large-scale SoC testing device based on the multi-FPGA chip cascade is characterized by comprising: And a memory communicatively coupled to the at least one processor, wherein the memory stores instructions executable by the at least one processor for performing the multi-FPGA chip cascade-based large SoC test method of any of claims 1-8.
  10. 10. A non-transitory computer storage medium storing computer executable instructions for execution by one or more processors to perform the method of multi-FPGA chip cascading based large SoC testing as claimed in any of claims 1-8.

Description

Large-scale SoC test method and device based on multi-FPGA chip cascading Technical Field The invention relates to the technical field of SoC test, in particular to a large-scale SoC test method and device based on multi-FPGA chip cascading. Background In System on Chip (SoC) design, prototype verification of the SoC is an indispensable step, register-TRANSFER LEVEL (RTL) simulation can accurately test details of the SoC, and a field programmable gate array (Filed Programmable GATE ARRAY, FPGA) Chip has the advantages of high iteration speed, low iteration cost, high universality and the like, and is more speed-advantageous compared with RTL simulation in the prototype verification of the SoC design in terms of integral performance of the SoC, joint debugging among various modules, use case test of complex scenes, pressure test of boundary conditions and the like. With the rapid development of the chip industry, the scale of the SoC is rapidly enlarged, and the problems of insufficient resource capacity or difficult timing convergence and the like of a single FPGA chip at present cause that the single FPGA chip cannot support the verification of a complete SoC system, so that a method for carrying out the complete SoC verification by using a plurality of FPGA chips is required to be designed. In the Field Programmable Gate Array (FPGA) prototype verification scene at the present stage, a plurality of test versions are obtained by cutting an internal module of the SoC, all the test versions are tested one by using a single FPGA chip, so that the effect of carrying out complete function test on each module in the SoC is achieved, namely, the complete function test of the module in the SoC is realized in stages, and each test version only comprises part of the modules in the SoC, so that the test mode is different from the actual SoC, the test coverage rate of the module in the SoC is insufficient, the condition of verification escape occurs, and the risk of a flow sheet is increased. In view of this, overcoming the drawbacks of the prior art is a problem to be solved in the art. Disclosure of Invention Aiming at the defects or improvement demands of the prior art, the invention provides a large SoC testing method and device based on multi-FPGA chip cascading, which can get rid of the problem of resource limitation of a single FPGA chip, so that the function test of a complete large SoC system is realized by utilizing a plurality of cascaded FPGA chips. The embodiment of the invention adopts the following technical scheme: In a first aspect, the invention provides a large SoC test method based on multi-FPGA chip cascading, wherein the large SoC comprises a plurality of modules, in particular, the resource occupancy rate of each module on the SoC is evaluated; According to the resource occupancy rate of each module, mapping each module onto a plurality of FPGA chips respectively; Connecting two adjacent FPGA chips in series in sequence to realize cascade connection of all the FPGA chips; respectively carrying out synthesis and implementation processing on each FPGA design, generating a bit stream file, and burning the bit stream file to each FPGA chip; after all the FPGA chips are reset according to the correct time sequence, all the FPGA chips are used as a whole for SoC function test. Preferably, the mapping each module onto a plurality of FPGA chips according to the resource occupancy rate of each module includes: Acquiring the resource occupancy rate of each module; And determining the mapped FPGA chips according to the resource occupancy rate of each module in sequence from high to low so as to map each module onto a plurality of FPGA chips, wherein each FPGA chip comprises one or more modules, and the sum of the resource occupancy rates of all the modules on the FPGA chip is smaller than or equal to the resource threshold value of the FPGA chip. Preferably, the two adjacent FPGA chips are sequentially connected in series to perform data communication between the two adjacent FPGA chips, so as to implement cascade connection of all FPGA chips, including: For an FPGA chip, the FPGA chip comprises an internal module and an IP core, wherein serial data generated by the module is transmitted to the IP core through an on-chip bus; Converting the parallel data into serial data through a transceiver, and leading out the serial data through an I/O pin and an external expansion interface of the FPGA chip; transmitting the serial data led out from the external expansion interface to another FPGA chip adjacent to the FPGA chip through a high-speed serial link to obtain a data path of two adjacent FPGA chips; And connecting two adjacent FPGA chips in sequence according to the data path so as to realize cascade connection of all the FPGA chips. Preferably, the on-chip bus includes a first on-chip bus and a second on-chip bus, the method further comprising: Determining bus protocol types of modules in two adjacent FPGA