CN-121997857-A - Integrated verification system and method based on multi-protocol bridging

CN121997857ACN 121997857 ACN121997857 ACN 121997857ACN-121997857-A

Abstract

The present disclosure relates to the field of integrated circuit design technology, and in particular, to an integrated verification system and method based on multi-protocol bridging. And dynamically converting the instruction of the first communication interface into a bottom layer target protocol time sequence by configuring a control and bridging conversion module, thereby constructing a unified register access entry. The design effectively avoids the redundant work that drive codes are required to be written for each peripheral protocol in the traditional verification. Meanwhile, in the system-level simulation stage, the mechanism thoroughly decouples the high-level test sequence from the bottom-level physical protocol, reduces time expenditure caused by frequent development and mounting of different interfaces, and improves the cross-level multiplexing rate and the overall simulation efficiency of the verification environment. After the built-in self-checking test engine is introduced, the system can automatically generate continuous target access addresses and expected test data internally through hardware logic according to preset instructions. The automatic internal excitation generation can improve the automation level and the sieve sheet efficiency of the chip mass production test stage.

Inventors

LI MINGXIN
LAI JUNSHENG

Assignees

皇虎测试科技(深圳)有限公司

Dates

Publication Date: 20260508
Application Date: 20260408

Claims (10)

1. An integrated authentication system based on multiprotocol bridging, the system comprising: The configuration control module is used for receiving a test configuration instruction through the first communication interface, and analyzing the test configuration instruction to acquire a target address interval, a data generation rule, a designated writing protocol type and a designated reading protocol type; The self-checking test engine is connected with the configuration control module and is used for automatically generating a target access address and expected write-in data through hardware logic based on the target address interval and the data generation rule when receiving an automatic test trigger instruction; The bridge conversion and caching module comprises a first storage unit and a second storage unit, and is used for converting the expected write data into a first timing sequence signal based on the write protocol type, sending the first timing sequence signal to the target access address of the equipment to be tested and storing the expected write data into the first storage unit; And the hardware comparison module is used for sequentially extracting the data in the first storage unit and the second storage unit for comparison, updating the verification state indication information of the internal state register according to the comparison result, and obtaining and executing the target screening control action by the external equipment, wherein the reading protocol type is the same as or different from the writing protocol type.
2. The system of claim 1, wherein the configuration control module has a configuration register set mapped therein, the configuration register set comprising at least: The first control register is used for configuring the working mode of the system into a normal read-write mode or an automatic self-checking test mode; The second control register is used for configuring a start address and an end address of the target address interval, the data generation rule and a single protocol test enabling state in the automatic self-checking test mode; A third control register configured to separately configure the specified write protocol type and the specified read protocol type, respectively, when the read protocol type is different from the write protocol type; And the fourth state register is particularly used for recording the target access address with the current error into an error address field when judging that the expected write-in data is inconsistent with the corresponding actual return data, recording the corresponding expected write-in data and the corresponding actual return data into an expected data field and an actual data field respectively, performing hardware accumulation operation on an internal error counter, and receiving global flag bits representing the self-checking completion and self-checking passing state after all the comparison in the target address interval is completed.
3. The system of claim 2, wherein the self-test engine has integrated therein address generation logic and data generation logic; When the first control register is configured to indicate the automated self-test mode, the address generation logic generates the incremented target access address by hardware stepping based on the start address and end address in the second control register; And the data generation logic generates the expected write-in data corresponding to the current target access address through an address mapping mode, an address inversion mode or a fixed characteristic value output mode according to the data generation rule configured in the second control register.
4. The system of claim 1, wherein the bridge translation and buffering module has integrated therein multi-protocol timing generation logic configured to: Responding to the write-in protocol type or the read-out protocol type as a first preset high-speed bus protocol, and carrying out time sequence transmission on the input data to be written in and the target access address; And in response to the writing protocol type or the reading protocol type being a low-speed serial peripheral protocol, packaging the expected writing data into corresponding serial data frames through a built-in protocol conversion engine or analyzing the received serial data frames into the actual return data, wherein the low-speed serial peripheral protocol comprises a serial peripheral interface protocol or an internal integrated circuit bus protocol.
5. The system of claim 1, wherein the first storage unit and the second storage unit are asynchronous memory banks that are independent of each other; In the case where the data transfer rates of the write protocol type and the read protocol type do not match, the hardware comparison module is configured to: monitoring the data writing state of the first storage unit and the second storage unit in real time; When detecting that at least one complete data is stored in each of the first storage unit and the second storage unit, respectively extracting first information in the first storage unit and the second storage unit for first-round logic comparison; and extracting next information from the first storage unit and the second storage unit in turn according to the data interaction sequence for iterative comparison so as to eliminate interference of a speed difference between the first time sequence signal and the second time sequence signal on a hardware comparison process.
6. The system of claim 1, wherein the first communication interface is an APB interface, and the configuration control module receives the test configuration instruction through the APB interface and implements multiplexing of a top layer interface; the writing protocol type and the reading protocol type are low-speed serial peripheral protocols and are respectively and independently configured as SPI protocols or I2C protocols; The bridging conversion and caching module is specifically configured to automatically pack and convert the transaction level configuration instruction issued based on the APB interface into a bottom data frame conforming to the SPI protocol or the I2C protocol for output.
7. An integrated verification method based on multiprotocol bridging, applied to the integrated verification system based on multiprotocol bridging as recited in any one of claims 1 to 6, comprising: Receiving a test configuration instruction through a first communication interface, and analyzing the test configuration instruction to obtain a target address interval, a data generation rule, a designated writing protocol type and a designated reading protocol type; When an automatic test trigger instruction is received, automatically generating a target access address and expected write data through hardware logic based on the target address interval and the data generation rule; The method comprises the steps of converting the expected write data into a first time sequence signal based on the write protocol type, sending the first time sequence signal to the target access address of the equipment to be tested, and storing the expected write data into a first storage unit; And sequentially extracting the data in the first storage unit and the second storage unit for comparison, and updating the verification state indication information of the internal state register according to the comparison result so as to obtain and execute the target screening control action by the external equipment, wherein the reading protocol type is the same as or different from the writing protocol type.
8. An electronic device, comprising: a memory and a processor, said memory and said processor being communicatively coupled to each other, said memory having stored therein computer instructions that, upon execution, cause said processor to perform the multiprotocol bridging-based integrated authentication method of claim 7.
9. A computer-readable storage medium having stored thereon computer instructions for causing a computer to perform the multiprotocol bridging-based integrated authentication method of claim 7.
10. A computer program product comprising computer instructions for causing a computer to perform the multiprotocol bridging-based integrated authentication method of claim 7.

Description

Integrated verification system and method based on multi-protocol bridging Technical Field The invention relates to the technical field of integrated circuit design, in particular to an integrated verification system and method based on multi-protocol bridging. Background With the continuous complexity of System on Chip (SoC) design and Chip verification, multi-interface communication plays a central role in System-on-Chip interaction, and register configuration of external devices through different interfaces has become a standard function. With this, the verification and testing environment of such multi-protocol complex systems face serious challenges such as complicated test case development, low factory testing efficiency, etc. In the related art, there are often cases where test resources are consumed too much and verification mechanisms are weak. Therefore, how to unify register access entries, reduce multi-protocol verification overhead, and improve the automatic self-checking and multi-interface cross-verification capability of the registers in the chip becomes a problem to be solved. Disclosure of Invention In view of this, the present invention provides an integrated verification system and method based on multi-protocol bridging, so as to solve the problem of how to improve the automatic self-checking and multi-interface cross-verification capability of the registers in the chip while unifying the access entry of the registers and reducing the multi-protocol verification overhead. An aspect of the present disclosure provides an integrated authentication system based on multiprotocol bridging, the system comprising: the configuration control module is used for receiving a test configuration instruction through the first communication interface, analyzing the test configuration instruction to obtain a target address interval, a data generation rule, a designated writing protocol type and a designated reading protocol type; The self-checking test engine is connected with the configuration control module and is used for automatically generating a target access address and expected write-in data through hardware logic based on a target address interval and a data generation rule when an automatic test trigger instruction is received; The bridge conversion and caching module comprises a first storage unit and a second storage unit, and is used for converting expected write data into a first time sequence signal based on a write protocol type, sending the first time sequence signal to a target access address of the equipment to be tested, and storing the expected write data into the first storage unit; The hardware comparison module is used for sequentially extracting data in the first storage unit and the second storage unit for comparison, updating verification state indication information of the internal state register according to a comparison result, and enabling the external equipment to acquire and execute target screening control actions, wherein the reading protocol type is the same as or different from the writing protocol type. The disclosure also provides an integrated verification method based on multi-protocol bridging, which is applied to the integrated verification system based on multi-protocol bridging, and the method comprises the following steps: Receiving a test configuration instruction through a first communication interface, and analyzing the test configuration instruction to acquire a target address interval, a data generation rule, a designated writing protocol type and a designated reading protocol type; when an automatic test trigger instruction is received, automatically generating a target access address and expected write data through hardware logic based on a target address interval and a data generation rule; the method comprises the steps of converting expected write data into a first time sequence signal based on a write protocol type, sending the first time sequence signal to a target access address of equipment to be tested, storing the expected write data into a first storage unit, generating a second time sequence signal based on a read protocol type, acquiring actual return data from the target access address, and storing the actual return data into a second storage unit; and sequentially extracting data in the first storage unit and the second storage unit for comparison, and updating verification state indication information of an internal state register according to a comparison result so as to obtain and execute target screening control actions by external equipment, wherein the reading protocol type is the same as or different from the writing protocol type. The disclosure also provides an electronic device, which comprises a memory for storing a computer program and a processor for implementing the steps of the integrated verification method based on multi-protocol bridging when the computer program is executed. In another aspect, the disclosure further pro