CN-121997858-A - SOC (system on chip) -oriented simulation verification acceleration method

CN121997858ACN 121997858 ACN121997858 ACN 121997858ACN-121997858-A

Abstract

The embodiment of the invention relates to the technical field of integrated circuits and chip designs, and provides an SOC-chip-oriented simulation verification acceleration method, which comprises the steps of obtaining a simulation verification request of an SOC chip; responding to the simulation verification request, connecting a processor core of the SOC chip with peripheral equipment of the SOC chip through a preset circuit configuration interface, wherein the peripheral equipment comprises a plurality of registers, initializing the registers through a configuration register parameter sequence recorded in a test file and the circuit configuration interface, and performing simulation verification on the SOC chip after the initialization operation of the registers is completed. Therefore, the configuration interface of the processor core and the high-speed peripheral controller is bypassed, the value of the register is directly loaded, the participation of an operating system and the processor core is not needed, hardware resources are saved, the time for initializing peripheral equipment is shortened, and the simulation verification efficiency of the SOC chip is improved.

Inventors

JIANG YANDE
ZHANG RUIKANG
AI YONGBAO
MA JINGBO
HUANG CHENGLONG
ZHANG GUANGDA
DAI HUADONG
WANG HUIQUAN
ZHAO XIA
FANG JIAN
Yi Pinjun

Assignees

中国人民解放军军事科学院国防科技创新研究院

Dates

Publication Date: 20260508
Application Date: 20241108

Claims (10)

1. The SOC-oriented simulation verification acceleration method is characterized by comprising the following steps of: acquiring an analog verification request of the SOC chip; Responding to the simulation verification request, and connecting a processor core of the SOC chip with peripheral equipment of the SOC chip through a preset circuit configuration interface, wherein the peripheral equipment comprises a plurality of registers; Initializing the registers through a configuration register parameter sequence recorded in a test file and the circuit configuration interface; and performing simulation verification on the SOC chip after the initialization operation of the plurality of registers is completed.
2. The method of claim 1, wherein the connecting the processor core of the SOC chip with the peripheral device of the SOC chip through a preset circuit configuration interface in response to the analog verification request comprises: presetting a configuration circuit for the peripheral equipment; and responding to the simulation verification request, loading a peripheral device value of the configuration circuit through an AHB bus, and connecting a processor core of the SOC chip with the peripheral device.
3. The method of claim 1, wherein after the obtaining the simulated verification request of the SOC chip, comprising: The phase locking ring is controlled to lock and electrify the peripheral equipment through the test excitation applied in the test file; Resetting the locked and powered peripheral equipment, and clearing data and states in the peripheral equipment.
4. A method according to claim 3, wherein initializing the plurality of registers by the sequence of configuration register parameters and the circuit configuration interface described in the test file comprises: Detecting whether the level of a reset signal for resetting the locked and powered-on peripheral equipment is raised to a preset threshold value or not; If yes, detecting the frequency of the peripheral equipment; And initializing the registers through a configuration register parameter sequence recorded in a test file and the circuit configuration interface based on the frequency of the peripheral equipment.
5. The method of claim 4, wherein initializing the plurality of registers via the sequence of configuration register parameters and the circuit configuration interface described in the test file based on the frequency of the peripheral device comprises: if the frequency of the peripheral equipment reaches a preset frequency threshold value, initializing register configuration by a high-frequency controller; And if the frequency of the peripheral equipment does not reach the preset frequency threshold value, initializing register configuration by the low-frequency controller.
6. The method of claim 5, wherein performing analog verification on the SOC chip after the plurality of register initialization operations are completed, comprises: after the initialization operation is completed on the plurality of registers, defining a programmable mode of the plurality of registers; after defining the programmable modes of the registers, performing ZQ calibration on termination resistance values of an internal address line and a command line of circuit design of the registers by using resistance values of reference resistors; And performing ZQ calibration on termination resistance values of an address line and a command line in circuit design of the registers, and performing simulation verification on the SOC chip.
7. An SOC-chip-oriented simulation verification acceleration device, comprising: The acquisition module is used for acquiring an analog verification request of the SOC chip; the response module is used for responding to the simulation verification request and connecting the processor core of the SOC chip with peripheral equipment of the SOC chip through a preset circuit configuration interface, wherein the peripheral equipment comprises a plurality of registers; the initialization module is used for initializing the plurality of registers through the configuration register parameter sequences recorded in the test file and the circuit configuration interface; and the simulation verification module is used for performing simulation verification on the SOC chip after the initialization operation of the plurality of registers is completed.
8. An electronic device comprising a memory, a processor and a computer program stored on the memory and executable on the processor, characterized in that the processor implements the SOC-chip-oriented simulated verification acceleration method of any of claims 1 to 6 when the computer program is executed by the processor.
9. A non-transitory computer readable storage medium having stored thereon a computer program, wherein the computer program when executed by a processor implements the SOC-chip oriented analog verification acceleration method of any of claims 1 to 6.
10. A computer program product comprising a computer program, characterized in that the computer program, when executed by a processor, implements the SOC-chip-oriented simulation verification acceleration method of any of claims 1 to 6.

Description

SOC (system on chip) -oriented simulation verification acceleration method Technical Field The invention relates to the technical field of integrated circuits and chip design, in particular to an SOC-oriented simulation verification acceleration method. Background At present, the design scale of a System On Chip (SOC) increases exponentially, and the number of logic gates and the number of functional modules included in the design are continuously increased, so is the design complexity. Therefore, the simulation verification difficulty of the chip before tape out streaming is greater, the simulation verification time is longer and longer, and the cost is increased. In the whole SOC chip simulation verification process, the initialization of high-speed peripheral equipment (such as a DDR controller and a PCIE controller) is an indispensable link. The high-speed peripheral equipment is initialized for a long time, so that the efficiency of the simulation verification of the SOC chip is greatly influenced, and the convergence time of the simulation verification of the SOC chip is limited. In initializing the high-speed peripheral device, a command for configuring a register is required to be sent through a processor core (CPU core) under the management of an operating system to configure a register of a high-speed peripheral interface circuit (e.g., a DDR controller circuit, a PCIE controller circuit). Since the number of registers of the high-speed peripheral interface circuit is very large, for example, 8000 registers of the DDR interface circuit need to be configured, it takes a long time to initialize the high-speed peripheral device. Therefore, how to accelerate the SOC chip simulation verification process is a technical difficulty faced by current SOC chip simulation verification. Disclosure of Invention The invention provides an SOC chip simulation verification acceleration method, which is used for solving the defects that the time consumption for initializing high-speed peripheral equipment is long and the simulation verification efficiency of an SOC chip is influenced when the SOC chip is simulated and verified in the prior art, shortening the time for initializing the peripheral equipment and improving the simulation verification efficiency of the SOC chip. The invention provides an SOC-chip-oriented simulation verification acceleration method, which comprises the following steps: acquiring an analog verification request of the SOC chip; Responding to the simulation verification request, and connecting a processor core of the SOC chip with peripheral equipment of the SOC chip through a preset circuit configuration interface, wherein the peripheral equipment comprises a plurality of registers; Initializing the registers through a configuration register parameter sequence recorded in a test file and the first circuit configuration interface; and performing simulation verification on the SOC chip after the initialization operation of the plurality of registers is completed. In one possible embodiment, the method further comprises: presetting a configuration circuit for the peripheral equipment; and responding to the simulation verification request, loading a peripheral device value of the configuration circuit through an AHB bus, and connecting a processor core of the SOC chip with the peripheral device. In one possible embodiment, the method further comprises: The phase locking ring is controlled to lock and electrify the peripheral equipment through the test excitation applied in the test file; Resetting the locked and powered peripheral equipment, and clearing data and states in the peripheral equipment. In one possible embodiment, the method further comprises: Detecting whether the level of a reset signal for resetting the locked and powered-on peripheral equipment is raised to a preset threshold value or not; If yes, detecting the frequency of the peripheral equipment; and initializing the registers through the configuration register parameter sequence recorded in the test file and the first circuit configuration interface based on the frequency of the peripheral equipment. In one possible embodiment, the method further comprises: if the frequency of the peripheral equipment reaches a preset frequency threshold value, initializing register configuration by a high-frequency controller; And if the frequency of the peripheral equipment does not reach the preset frequency threshold value, initializing register configuration by the low-frequency controller. In one possible embodiment, the method further comprises: after the initialization operation is completed on the plurality of registers, defining a programmable mode of the plurality of registers; after defining the programmable modes of the registers, performing ZQ calibration on termination resistance values of an internal address line and a command line of circuit design of the registers by using resistance values of reference resistors; And perf