CN-121997860-A - Chip verification system, method and related equipment

Abstract

In the chip verification system, verification environments of a plurality of first tested designs are integrated into the first verification environments, and compared with the mode that the corresponding verification environments are respectively arranged in the first tested environments, the number of the verification environments can be reduced, so that the integration difficulty between the verification environments is reduced, and the management and debugging difficulty is reduced. And the first interconnection component is positioned in the first verification environment or the second verification environment, the first application program interface is used for realizing the connection between the first tested design and the second test, the second interconnection component is positioned in the first verification environment or the second verification environment, and the second application program interface is used for realizing the connection between the first reference model and the second reference model, so that the communication overhead between the first verification environment and the second verification environment is reduced, and the simulation verification efficiency is improved.

Inventors

• LV CHAO

Assignees

• 海光信息技术股份有限公司

Dates

Publication Date

20260508

Application Date

20251224

Claims (11)

1. 1.A chip authentication system, comprising: A first verification environment corresponding to a plurality of first designs under test, comprising a plurality of first reference models of the first designs under test, the plurality of first reference models being arranged in one-to-one correspondence with the plurality of first designs under test, and a first environment verification component for applying a first test stimulus to at least the first designs under test and the first reference models; A second verification environment corresponding to a second design under test, comprising a second reference model of the second design under test, and a second environment verification component for applying a second test stimulus to at least the second design under test and the second reference model, the second verification environment being different from the first verification environment; a first interconnection component located in the first verification environment or the second verification environment for enabling connection between the plurality of first tested designs and the second tested designs by means of a first application program interface; and a second interconnection component, located in the first verification environment or the second verification environment, for implementing connection between the plurality of first reference models and the second reference model through a second application program interface.
2. 2. The chip verification system of claim 1, further comprising at least one of a plurality of third reference models in the first verification environment and a fourth reference model in the second verification environment, the plurality of third reference models being arranged in one-to-one correspondence with the plurality of first designs under test and being identical to the first reference models, respectively, and the fourth reference model being identical to the second reference model; The first interconnection component is used for realizing connection between the first tested designs and the second tested designs through the first application program interface under the condition of carrying out joint simulation verification on the first tested designs and the second tested designs, is also used for realizing connection between the third reference models and the second tested designs through the first application program interface under the condition of carrying out independent simulation verification on the second tested designs, and is also used for realizing connection between the first tested designs and the fourth reference models through the first application program interface under the condition of carrying out independent simulation verification on the first tested designs.
3. 3. The chip verification system of claim 2, wherein switching between the scenario of joint simulation verification of the plurality of first designs under test and the second designs under test, the scenario of individual simulation verification of the second designs under test, and the scenario of individual simulation verification of the plurality of first designs under test is controlled by a preset full-chip parameter.
4. 4. The chip authentication system of claim 1, wherein the first application program interface and the second application program interface are each provided by a distributed simulation tool.
5. 5. The chip verification system of claim 1, wherein the first device under test is a compute core chip and the second device under test is a control chip.
6. 6. A chip authentication method, comprising: Constructing a joint simulation verification environment for joint simulation verification of a plurality of first tested designs and a second tested design, wherein the joint simulation verification environment comprises a first verification environment corresponding to the first tested designs, a plurality of first reference models comprising the first tested designs, a first environment verification component for applying first test excitation to at least the first tested designs and the first reference models, and a first environment verification component for generating a first test excitation according to the first reference models; a second verification environment corresponding to a second design under test, comprising a second reference model of the second design under test, and a second environment verification component for applying a second test stimulus to at least the second design under test and the second reference model, the second verification environment being different from the first verification environment; the system comprises a first verification environment, a second verification environment, a first interconnection component, a second interconnection component, a first reference model and a second reference model, wherein the first interconnection component is positioned in the first verification environment or the second verification environment and is used for realizing connection between the first tested designs and the second tested designs through a first application program interface; and adopting the joint simulation verification environment to perform joint simulation verification on the first tested design and the second tested design.
7. 7. The chip authentication method of claim 6, further comprising at least one of: Constructing a verification environment for performing independent simulation verification on the second tested design, and performing independent simulation verification on the second tested design; the environment for performing individual simulation verification on the second tested design comprises a first verification environment corresponding to a plurality of first tested designs, a first environment verification component, a second verification environment corresponding to the second tested designs, a second environment verification component, a first interconnection component, a second interconnection component and a second interconnection component, wherein the first verification environment comprises a plurality of first reference models and a plurality of third reference models of the first tested designs, the plurality of first reference models and the plurality of third reference models are respectively arranged in one-to-one correspondence with the plurality of first tested designs, and the first environment verification component is used for applying first test excitation to the plurality of first reference models and the plurality of third reference models; The method comprises the steps of constructing a verification environment for performing independent simulation verification on a plurality of first tested designs and performing independent simulation verification on the plurality of first tested designs, wherein the verification environment for performing independent simulation verification on the plurality of first tested designs comprises a first verification environment corresponding to the plurality of first tested designs and a first environment verification component, a first interconnection component and a second interconnection component, wherein the first reference model comprises a plurality of first reference models of the first tested designs, the plurality of first reference models are respectively arranged in one-to-one correspondence with the plurality of first tested designs, the first environment verification component is used for applying first test excitation to at least the first tested designs and the first reference models, the second verification environment corresponding to the second tested designs comprises a second reference model and a fourth reference model of the second tested designs, the second environment verification component is used for applying second test excitation to the second reference models and the fourth reference models, the first interconnection component is positioned in the first verification environment or the second verification environment, the first interconnection component is used for realizing connection between the first interconnection component and the first reference model and the second application program by means of the first interconnection component, and the second interconnection component is used for realizing the verification between the first environment and the first interconnection component and the first reference model.
8. 8. The chip verification method according to claim 7, wherein switching between a scenario of joint simulation verification of the plurality of first tested designs and the second tested designs, a scenario of individual simulation verification of the second tested designs and a scenario of individual simulation verification of the plurality of first tested designs is controlled by preset full-chip parameters.
9. 9. A computer device comprising a memory and a processor, the memory storing one or more computer instructions, wherein the one or more computer instructions are executed by the processor to implement the chip authentication method of any of claims 6-8.
10. 10. A computer program product comprising computer program/instructions which, when executed by a processor, is adapted to carry out a chip authentication method according to any one of claims 6 to 8.
11. 11. A storage medium storing one or more computer instructions for implementing the chip authentication method according to any one of claims 6 to 8.

Description

Chip verification system, method and related equipment Technical Field The embodiment of the invention relates to the field of chip verification, in particular to a chip verification system, a method and related equipment. Background Functional verification plays a vital role in integrated circuit (INTEGRATED CIRCUIT, IC) design, the primary purpose of which is to ensure correctness of the integrated circuit design and compliance with design specifications. The simulation verification is a verification method widely adopted in the function verification of integrated circuit design, a verification platform is built based on a System Verilog (SV) language, and directional test excitation is written to perform simulation verification on a tested design (Design Under Test, DUT). With the rapid development of semiconductor technology, the technology of the core particle (Chiplet) integrates transistors to manufacture the core particle with specific functions, and then the core particle is integrated through the semiconductor technology according to application requirements, so that the product yield of a chip can be effectively improved, the overall manufacturing cost of the chip can be obviously reduced, and the chip is a star technology in recent years in the semiconductor industry. With the vigorous development of core technology, how to reduce the difficulty of management and debugging and improve the efficiency of joint simulation verification among a plurality of tested designs becomes a technical problem to be solved in the field. Disclosure of Invention The embodiment of the invention solves the problem of providing a chip verification method and related equipment, which can reduce the difficulty of management and debugging and improve the efficiency of joint simulation verification among a plurality of tested designs while realizing joint simulation verification among the plurality of tested designs. To solve the above problems, an embodiment of the present invention provides a chip verification system, including: A first verification environment corresponding to a plurality of first designs under test, comprising a plurality of first reference models of the first designs under test, the plurality of first reference models being arranged in one-to-one correspondence with the plurality of first designs under test, and a first environment verification component for applying a first test stimulus to at least the first designs under test and the first reference models; A second verification environment corresponding to a second design under test, comprising a second reference model of the second design under test, and a second environment verification component for applying a second test stimulus to at least the second design under test and the second reference model, the second verification environment being different from the first verification environment; a first interconnection component located in the first verification environment or the second verification environment for enabling connection between the plurality of first tested designs and the second tested designs by means of a first application program interface; and a second interconnection component, located in the first verification environment or the second verification environment, for implementing connection between the plurality of first reference models and the second reference model through a second application program interface. Optionally, the chip verification system further comprises at least one of a plurality of third reference models in the first verification environment and a fourth reference model in the second verification environment, wherein the plurality of third reference models are arranged in one-to-one correspondence with the plurality of first tested designs and are respectively identical to the first reference models, and the fourth reference model is identical to the second reference model; The first interconnection component is used for realizing connection between the first tested designs and the second tested designs through the first application program interface under the condition of carrying out joint simulation verification on the first tested designs and the second tested designs, is also used for realizing connection between the third reference models and the second tested designs through the first application program interface under the condition of carrying out independent simulation verification on the second tested designs, and is also used for realizing connection between the first tested designs and the fourth reference models through the first application program interface under the condition of carrying out independent simulation verification on the first tested designs. Optionally, the switching between the scenario of performing joint simulation verification on the first tested designs and the second tested designs, the scenario of performing individual simulation verification on the second tested