CN-121997863-A - Artificial intelligence chip and test access method for same

CN121997863ACN 121997863 ACN121997863 ACN 121997863ACN-121997863-A

Abstract

The present disclosure relates to artificial intelligence chips and test access methods for artificial intelligence chips. Based on the application, the on-chip function module of the artificial intelligent chip can be provided with a synchronous conversion circuit with simplified control logic than JTAG logic, a conversion controller of the synchronous conversion circuit can control the test signal written by an external host through a JTAG interface to synchronize to the signal of a signal synchronization register of the synchronous conversion circuit according to the bus clock of an AMBA bus based on the control state maintained by the external host, and can also control the data transmission of the test signal in the signal synchronization register to the function register through the AMBA bus in the artificial intelligent chip. Thus, the on-chip functional module of the artificial intelligence chip may not need to have JTAG logic, thereby helping to reduce the circuit area of the on-chip functional module and thus helping to reduce the circuit area of the artificial intelligence chip.

Inventors

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Assignees

上海壁仞科技股份有限公司

Dates

Publication Date: 20260508
Application Date: 20260410

Claims (10)

1. An artificial intelligence chip, comprising: a JTAG interface; A test driving module, including a test data register, the test data register being configured to store a test signal written by an external host through the JTAG interface and record a control state maintained by the external host through the JTAG interface, the test signal being used for a test access to a functional register inside the artificial intelligence chip, the control state including a selected state and an active state, the selected state being set by the external host to be active during a period in which the external host initiates the test access, the active state being set by the external host to be active during a period in which the external host outputs the test signal to the JTAG interface, and being set to be inactive by the external host after an output of the test signal to the JTAG interface is completed; An on-chip functional module, the on-chip functional module comprising a synchronous conversion circuit, the synchronous conversion circuit comprising a signal synchronization register and a conversion controller, the signal synchronization register being connected to the functional register by an AMBA bus, the conversion controller being configured to: Enabling signal synchronization of the test signal in the test data register to the signal synchronization register based on a bus clock of the AMBA bus during a period in which the selected state is asserted by the external host; In response to a change in the active state from active to inactive, signal transmission of the test signal in the signal synchronization register to the functional register via the AMBA bus is enabled to enable the test access to the functional register.
2. The artificial intelligence chip of claim 1, wherein the artificial intelligence chip comprises, The transition controller is specifically configured to implement enabling control of the signal synchronization and the signal transmission by maintaining a state machine, the state machine comprising an initial state, a ready state, a set state, an enabled state, wherein: When the state machine is in the initial state, transitioning from the initial state to the ready state in response to a change in the selected state from invalid to valid to trigger the transition controller to enable the signal synchronization; When the state machine is in the ready state, transitioning from the ready state to the initial state in response to a change in the selected state from valid to invalid; when the state machine is in the ready state, transitioning from the ready state to the set state in response to a change in the active state from active to inactive; When the state machine is in the set state, transitioning from the set state to the enabled state in response to completion of peripheral selection of the functional register via the AMBA bus to trigger the transition controller to enable the signaling; when the state machine is in the enabled state, transitions from the enabled state to the ready state in response to the signaling ending.
3. The artificial intelligence chip of claim 2, wherein the artificial intelligence chip comprises, When the state machine is in the initial state, the state machine is prohibited from migrating from the initial state to the ready state during a peripheral reset of the functional registers.
4. The artificial intelligence chip of any one of claims 1 to 3, further comprising: AMBA bus interface; The interface driving module is connected with the AMBA bus interface; The synchronous conversion circuit further comprises a multi-path selection switch, the multi-path selection switch is provided with a first bus port, a second bus port and a third bus port, the signal synchronization register is connected with the first bus port through the AMBA bus, the interface driving module is connected with the second bus port through the AMBA bus, the third bus port is connected with the functional register through the AMBA bus, and the first bus port and the second bus port are alternatively conducted with the third bus port.
5. The artificial intelligence chip of claim 4, wherein the artificial intelligence chip comprises, The conversion controller is further configured to: controlling the multiplexing switch to conduct the first bus port and the third bus port during the period that the selected state is set to be valid by the external host; And controlling the multiplexing switch to conduct the second bus port and the third bus port in a period that the selected state is reset to be invalid by the external host.
6. The artificial intelligence chip of any one of claims 1 to 3, wherein the test driver module further comprises a TAP controller in signal connection with the JTAG interface for writing the test signals and the control states received from an external host via the JTAG interface to the test data register.
7. The artificial intelligence chip according to any one of claim 1 to 3, wherein, The on-chip function modules are multiple, the test driving module comprises a plurality of test data registers which are correspondingly arranged with the on-chip function modules, and each on-chip function module is independently provided with a corresponding synchronous conversion circuit.
8. The test access method for the artificial intelligent chip is characterized in that the artificial intelligent chip comprises a JTAG interface, a test driving module and an on-chip function module, wherein the test driving module comprises a test data register, the test data register is used for storing a test signal written by an external host through the JTAG interface and recording a control state maintained by the external host through the JTAG interface, the test signal is used for testing access to a function register in the artificial intelligent chip, the control state comprises a selected state and an effective state, and the on-chip function module comprises a signal synchronization register, and the signal synchronization register is connected with the function register through an AMBA bus; the test access method comprises the following steps: Enabling signal synchronization of the test signal in the test data register to the signal synchronization register based on a bus clock of the AMBA bus during a period when the selected state is set to be valid by the external host, wherein the selected state is set to be valid by the external host during a period when the external host initiates the test access; And enabling signal transmission of the test signal in the signal synchronization register to the functional register through the AMBA bus in response to a change from valid to invalid of the valid state, so as to realize the test access to the functional register, wherein the valid state is set to be valid by the external host during the period that the external host outputs the test signal to the JTAG interface, and is set to be invalid by the external host after the output of the test signal to the JTAG interface is completed.
9. The test access method of claim 8, wherein, The test access method realizes the enabling control of the signal synchronization and the signal transmission through a maintenance state machine, wherein the state machine comprises an initial state, a preparation state, a setting state and an enabling state, and the method comprises the following steps: When the state machine is in the initial state, transitioning from the initial state to the ready state in response to a change in the selected state from invalid to valid to enable the signal synchronization; When the state machine is in the ready state, transitioning from the ready state to the initial state in response to a change in the selected state from valid to invalid; when the state machine is in the ready state, transitioning from the ready state to the set state in response to a change in the active state from active to inactive; When the state machine is in the set state, transitioning from the set state to the enabled state to enable the signaling in response to completion of a peripheral selection of the functional register over the AMBA bus; when the state machine is in the enabled state, transitions from the enabled state to the ready state in response to the signaling ending.
10. The test access method of claim 9, wherein, When the state machine is in the initial state, the state machine is prohibited from migrating from the initial state to the ready state during a peripheral reset of the functional registers.

Description

Artificial intelligence chip and test access method for same Technical Field The application relates to the field of AI (ARTIFICIAL INTELLIGENCE ) chips, in particular to an AI chip and a test access method for the AI chip. Background AI chips typically require testing (or debugging) at the DFT (Design for Testability ) stage after tape-out. The AI chip generally has a JTAG (Joint Test Action Group, joint test working group) interface for performing a test, and an external host of the AI chip may provide a test signal to an internal functional module of the AI chip through the JTAG interface, so that the functional module on the chip may perform a test access on a functional register of the AI chip by using the test signal, and further obtain a test result of the AI chip through the test access on the functional register. For the case of testing an AI chip through a JTAG interface, it is desirable for the on-chip functional modules in the AI chip to have JTAG logic, which may include, for example, a TAP (TEST ACCESS Port ). This leads to an increase in the circuit area of the on-chip functional module and thus the AI chip. Therefore, how to reduce the circuit area of the AI chip becomes a technical problem to be solved in the related art. It will be appreciated that the content of the "background art" section is intended to aid in understanding the present disclosure. Some (or all) of the disclosure in the background section may not be known to those of skill in the art. The disclosure in the background section is not presented for the purpose of providing a representation of what has been known to those of ordinary skill in the art prior to the present disclosure. Disclosure of Invention The embodiment of the application provides an AI chip and a test access method for the AI chip, which are beneficial to reducing the circuit area of the AI chip. In an embodiment of the present application, there is provided an AI chip including: a JTAG interface; A test driver module including a TDR (TEST DATA REGISTER ) for storing a test signal written by an external host through the JTAG interface and recording a control state maintained by the external host through the JTAG interface, the test signal for a test access to a functional register inside the artificial intelligence chip, the control state including a selected state and an active state, the selected state being set by the external host to be active during a period in which the external host initiates the test access, the active state being set by the external host to be active during a period in which the external host outputs the test signal to the JTAG interface, and being set to be inactive by the external host after an output of the test signal to the JTAG interface is completed; An on-chip functional module, the on-chip functional module comprising a synchronous conversion circuit, the synchronous conversion circuit comprising a signal synchronization register and a conversion controller, the signal synchronization register being connected to the functional register by an AMBA bus, the conversion controller being configured to: Enabling signal synchronization of the test signal in the TDR to the signal synchronization register based on a bus clock of the AMBA bus during a period in which the selected state is asserted by the external host; In response to a change in the active state from active to inactive, signal transmission of the test signal in the signal synchronization register to the functional register via the AMBA bus is enabled to enable the test access to the functional register. In some examples, optionally, the transition controller is specifically configured to enable control of the signal synchronization and the signal transfer by maintaining a state machine comprising an initial state, a ready state, a set state, an enabled state, wherein when the state machine is in the initial state, transition from the initial state to the ready state in response to a change from invalid to valid to trigger the transition controller to enable the signal synchronization, transition from the ready state to the initial state in response to a change from valid to invalid when the state machine is in the ready state, transition from the ready state to the enabled state in response to a change from valid to invalid when the state machine is in the ready state, transition from the ready state to the set state in response to a selection of the function register by the AMBA bus is completed when the state machine is in the set state, and enable signal transfer from the ready state to the enabled state when the state is completed in response to a selection of the AMBA transfer of the function register is completed. In some examples, optionally, when the state machine is in the initial state, the state machine is inhibited from migrating from the initial state to the ready state during a peripheral reset of the functional register. In some examples, optionally,