Search

CN-121997869-A - SAC algorithm-based LDMOS device electrical performance optimization method

CN121997869ACN 121997869 ACN121997869 ACN 121997869ACN-121997869-A

Abstract

The invention discloses an LDMOS device electrical performance optimization method based on a SAC algorithm, and belongs to the technical field of semiconductor power device design. The method comprises the steps of sampling within a technological parameter range, utilizing TCAD simulation to extract electrical characteristics to construct a data set, constructing a deep neural network proxy model and training, designing a state space, an action space and a reward function, constructing a SAC deep reinforcement learning framework, connecting the proxy model into the environment, and training the SAC model to obtain optimal technological parameters. According to the invention, the DNN agent model is used for replacing high-time-consumption simulation, and the SAC algorithm is combined for self-adaptive adjustment, so that the problem of difficulty in multi-objective collaborative optimization under a high-dimensional parameter space is effectively solved, the optimization period is obviously shortened, the collaborative improvement of the static and dynamic performances of the device is realized, and the optimization result has high reliability through circuit verification.

Inventors

  • XU KAI
  • Meng Baiying

Assignees

  • 浙江大学

Dates

Publication Date
20260508
Application Date
20260410

Claims (10)

  1. 1. The method for optimizing the electrical performance of the LDMOS device based on the SAC algorithm is characterized by comprising the following steps of: S1, data sampling is carried out in the design range of technological parameters, the generated device design scheme is subjected to LDMOS device technological simulation in TCAD software, the electrical characteristic parameters of the device are extracted from simulation results, and the design parameters and the electrical characteristic parameters of the LDMOS device are used as data sets; S2, constructing a deep neural network DNN as a proxy model, and training the deep neural network by using the generated data set; S3, designing a state space, an action space and a reward function of reinforcement learning, constructing a deep reinforcement learning neural network model based on a SAC algorithm, and accessing the trained agent model into a reinforcement learning environment; S4, training a SAC model to obtain optimal process design parameters output by a SAC algorithm, so as to obtain the LDMOS device with breakdown voltage, specific on-resistance and gate-drain charge synergistically optimized under the process conditions.
  2. 2. The method of claim 1, wherein in the step S1, the design range of the process parameters is defined as 14-dimensional process and structure parameters including STI oxide length, gate-to-STI overlap length, length of N drift region extending beyond STI, length of gate-over-P-channel, drift region first ion implantation energy and dose, drift region second ion implantation energy and dose, drift region third ion implantation energy and dose, channel region first ion implantation energy and dose, channel region second ion implantation energy and dose; the electrical performance parameters include breakdown voltage BV, specific on-resistance Ron, sp, and gate drain charge QGD.
  3. 3. The method for optimizing electrical performance of an LDMOS device based on a SAC algorithm according to claim 1, wherein in step S1, a latin hypercube sampling method is adopted for data sampling to generate 2000 groups of uniformly distributed experimental configuration schemes in a 14-dimensional parameter space; In the step S2, the deep neural network proxy model is a fully connected deep neural network, and the network structure includes: 14 neurons of the input layer corresponding to 14-dimensional technological parameters; The hidden layer is a four-layer full-connection layer, and the number of neurons is 512, 256, 128 and 64 respectively; 3 neurons for predicting BV, ron, sp and QGD; Activation function-the hidden layer adopts a ReLU activation function.
  4. 4. The method for optimizing electrical performance of LDMOS device based on SAC algorithm of claim 3, wherein in step S2, before training DNN proxy model, performing min-max normalization processing on all input parameters and output characteristics, and scaling data to [0,1] interval; the training method adopts five-fold cross validation, and the convergence criterion is that when the validation set determines coefficients And the training is terminated when there is no drop in the loss of 10 consecutive rounds.
  5. 5. The method for optimizing electrical performance of an LDMOS device based on a SAC algorithm according to claim 1, wherein in step S3, the state space is defined as a three-dimensional continuous space, which includes the current electrical performance of the device: ; The motion space is defined as a 14-dimensional continuous space corresponding to the adjustable 14-dimensional process parameters.
  6. 6. The method for optimizing electrical performance of an LDMOS device based on a SAC algorithm according to claim 1, wherein in the step S3, the design expression of the bonus function is: ; Wherein, the Based on static figure of merit The normalized static performance term is used to determine, Based on dynamic merit values Normalized dynamic performance terms; as a penalty term, a penalty is given to the set value when the breakdown voltage BV < 80.
  7. 7. The method for optimizing electrical performance of LDMOS device based on SAC algorithm of claim 1, wherein in step S3, the neural network architecture of SAC algorithm comprises: The strategy network is characterized by comprising a strategy network, an output layer, a storage layer and a storage layer, wherein the strategy network is characterized in that the input is a 3-dimensional state vector, and the output is the mean value and standard deviation of 14-dimensional action distribution; q-value network comprising two current action state value networks of Q0 and Q1, and 、 Two target action state value networks; The input dimension of the Q0 and Q1 networks is 3-dimensional state variable and 14-dimensional action variable, the hidden layer structure is [256,256], and the output is scalar Q value.
  8. 8. The method for optimizing electrical performance of LDMOS device according to claim 7, wherein in step S3, And (3) with Network parameters are synchronized to Q0 and Q1 networks by soft update mechanism, soft update rate ; The SAC algorithm also includes a temperature coefficient α, which is a trainable parameter, an initial value of 0.2, automatically adjusted to balance exploration and utilization by minimizing entropy loss.
  9. 9. The method for optimizing electrical performance of LDMOS device based on SAC algorithm of claim 1, wherein in step S3, the trained DNN agent model is encapsulated as a state transfer function of the environment: ; Environment receiving action Thereafter, a DNN proxy model is called to instantaneously predict the next state ; An experience playback buffer is set to 100000 transfer samples in capacity.
  10. 10. The method for optimizing electrical performance of an LDMOS device based on a SAC algorithm of claim 1, wherein said step S4 further comprises a verification step of: Constructing a switching circuit in TCAD mixed mode simulation, and extracting drain current of LDMOS switching behavior And drain-source voltage The energy consumed by switching transients of the device before and after optimization is compared over time to verify device performance.

Description

SAC algorithm-based LDMOS device electrical performance optimization method Technical Field The invention relates to the technical field of semiconductor power device design, in particular to an LDMOS device electrical performance optimization method based on a SAC algorithm. Background Currently, LDMOS (lateral double-diffused metal oxide semiconductor field effect transistor) devices are widely used in power integrated circuits due to their high voltage resistance and low on-resistance. However, the existing optimization method of the LDMOS device has the following defects and disadvantages: The existing LDMOS device optimization method only focuses on unilateral electrical performance, such as independently optimizing breakdown voltage or specific on-resistance, and cannot optimize the static performance and dynamic performance of the LDMOS. Because of the multiple process design parameters of the LDMOS device, each parameter affects the electrical performance, and there is a trade-off relationship between the electrical performance, for example, the breakdown voltage BV and the specific on-resistance Ron, sp are constrained by the silicon limit relationship, so that it is difficult to ensure that one is improved while ensuring that the performance of the other is not reduced. For complex parameter adjustment and optimization problems, the method of manually adjusting device parameters depending on physical principle analysis is difficult to cooperatively optimize for controlling a plurality of electrical properties, and TCAD simulation requires a lot of time. For the process for optimizing the LDMOS device, the existing population-based or genetic optimization algorithm has low dynamic adaptability, the whole optimization process needs to be restarted to adapt to changes, on-line adjustment is difficult, optimal solutions are difficult to search for high-dimensional data, the population is reevaluated in each iteration, historical evaluation results cannot be multiplexed, collaborative optimization for a plurality of targets depends on artificial weight setting or pareto sorting, and parameter adjustment cost is high. Therefore, there is a need for a multi-objective optimization method that can learn autonomously, adaptively adjust and efficiently solve the above-mentioned problems. Disclosure of Invention The invention aims to provide an optimization method for the electrical performance of an LDMOS device based on a SAC algorithm, which solves the problems that the static performance and the dynamic performance of the LDMOS device in the prior art are difficult to cooperatively optimize, and the optimization efficiency is low and the cost is high. In order to achieve the above purpose, the invention provides an optimization method for the electrical performance of an LDMOS device based on a SAC algorithm, which comprises the following steps: S1, data sampling is carried out within the design range of technological parameters, the generated device design scheme is subjected to LDMOS device technological simulation in SentaurusTCAD software, the electrical characteristic parameters of the device are extracted from simulation results, and the design parameters and the electrical characteristic parameters of the LDMOS device are used as data sets. S2, constructing a Deep Neural Network (DNN) serving as a proxy model, and training the deep neural network by using the generated data set. S3, designing a state space, an action space and a reward function of reinforcement learning, building a deep reinforcement learning neural network model based on a SAC algorithm, and accessing the trained agent model into a reinforcement learning environment. And S4, training the SAC (Soft resistor-Critic) model to obtain the optimal process design parameters output by the SAC algorithm, so as to obtain the LDMOS device with breakdown voltage, specific on-resistance and gate-drain charge synergistically optimized under the process condition. Further, the step S1 specifically includes: s11, defining a parameter space, and determining 14-dimensional process and structural parameters of the LDMOS device as design variables, wherein each parameter is in a certain constant interval. S12, experimental design sampling, namely generating 2000 groups of uniformly distributed experimental configuration schemes in the 14-dimensional parameter space by using a Latin hypercube sampling method, so as to ensure the full exploration of the parameter space. S13, TCAD process simulation, and establishing an LDMOS three-dimensional process simulation flow in SentaurusTCAD simulation software. The process simulation comprises the following key steps of carrying out three times of N drift region injection and annealing, wherein independent energy and dose parameters are adopted for each injection, then carrying out plasma etching, growing an oxide layer to form an STI structure, then carrying out gate oxide layer growth and polysilicon deposit