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CN-121997870-A - Derivation method of common-ground converter topology

CN121997870ACN 121997870 ACN121997870 ACN 121997870ACN-121997870-A

Abstract

The invention discloses a topology deriving method of a common-ground converter, and belongs to the technical field of converters. The method comprises the steps of determining the node number na and the switch number nb of the common ground converter topology, enabling the negative electrode of an input power supply and the negative electrode of an output end to be commonly grounded according to a double-grounding characteristic circuit, constructing an adjacent matrix according to the node number and the switch number, inserting capacitors and inductors into the adjacent matrix to obtain all topologies, carrying out isomorphic screening and feasibility screening on the obtained topologies, and eliminating the topologies of unnecessary categories according to the categories of requirements. The topology deduction method of the common-ground converter is completely based on adjacent matrix modeling, facilitates automatic generation and analysis through programming software, is strong in systematicness and clear in rules, can effectively eliminate invalid or redundant structures, and remarkably improves topology deduction efficiency and integrity.

Inventors

  • YAO ZHILEI
  • WU JINRONG
  • SHAO BEIBEI

Assignees

  • 上海海事大学

Dates

Publication Date
20260508
Application Date
20260128

Claims (7)

  1. 1. A method of deriving a topology of a common-ground converter, comprising the steps of: (1) Determining the node number na and the switch number nb of the common-ground converter topology, wherein the node number na and the switch number nb are at least 3 nodes and 2 switches; (2) According to the double-grounding characteristic circuit, the negative electrode of the input power supply and the negative electrode of the output end are grounded together and defined as a node 0; (3) Constructing an adjacent matrix according to the number of nodes and the number of switches, ensuring that a loop is formed between the adjacent matrix and the input power supply and the output end, and inserting switches between the nodes which are connected with each other; (4) Inserting a capacitance into the adjacency matrix, the capacitance allowing it to be placed between any two nodes; (5) Inserting an inductor into the adjacent matrix, introducing a new node into a branch needing to be inserted with the inductor in a node splitting mode, transferring an original branch element between the new node and one original node of the original branch, connecting the inductor between the new node and the other original node of the original branch, and setting 0 between the two elements of the original branch in the adjacent matrix; (6) Traversing all combinations of the steps (4) and (5) until all topologies are obtained, and carrying out isomorphic screening and feasibility screening on the obtained topologies to obtain legal topologies; (7) Based on the legal switch combination of the Boolean logic automatic enumeration legal topology, a depth-first search (DFS) traversal loop is combined, voltage gain, capacitance and voltage at two ends of the switch are calculated by utilizing a volt-second balance principle and kirchhoff voltage law, then class judgment of the topology as direct current or inversion is carried out, and the topology of the unnecessary class is removed according to the class of the requirement.
  2. 2. The method of claim 1, wherein the adjacency matrix is an N-order symmetric matrix for mathematically characterizing the topological connection between nodes in the circuit.
  3. 3. The method of deriving a common-ground converter topology according to claim 1, wherein when capacitances are inserted into said adjacent matrix in said step (4), the number of capacitances is independent of the number of nodes and the number of switches, and different capacitances can exist between two nodes at the same time.
  4. 4. The method of deriving a topology of a common-mode transformer according to claim 1, wherein, when a capacitor is inserted into the adjacent matrix in the step (4), one of the capacitors is connected to a parallel branch of an output load if the capacitor is in an independent structure, and the output terminal is directly connected to a power grid if the capacitor is in a grid-connected structure.
  5. 5. The method of deriving a common-ground converter topology according to claim 1, wherein the step (5) is specifically: (5.1) searching whether a loop consisting of an input source or a capacitor and a switch only exists, if the loop does not exist, directly executing the step (5.3), otherwise, inserting an inductor into one of all branches of a node contained in the loop, wherein the loop is a parallel branch for the node, and updating an adjacent matrix according to the following conditions: (a) If the inductor is inserted into the independent branch of the node, namely the branch is not a parallel branch, setting element 0 between the original two nodes of the branch in the adjacent matrix, transferring the element of the original branch to the space between the new node and the other original node of the original branch, and connecting the inductor between the new node and the node where the inductor needs to be inserted; (b) If the inductor is inserted into one of the parallel branches, the original elements of the parallel branches in the adjacent matrix should be split, elements between two nodes of the original parallel branches are rewritten into all branch elements without the inductor, the original elements of the branch added with the inductor migrate to between the new node and the other original node of the original branch, and the inductor is connected between the new node and the node to which the inductor needs to be inserted; (c) If the inductor is inserted into the independent branch and the parallel branch at the same time, the adjacent matrix is updated according to (a) and then the adjacent matrix of the parallel branch is updated according to (b); (5.2) searching whether a loop consisting of an input source or a capacitor and a switch exists in the topology corresponding to the updated adjacency matrix again, and if so, updating the adjacency matrix according to the step (5.1) until no such loop exists or the number of inserted inductances is equal to the number of given inductances; If the current inserted inductance number is equal to the given inductance number, ending the insertion of the inductance, otherwise, randomly selecting a node branch with a non-zero adjacent matrix element in any node to perform the inductance insertion, introducing a new node at a branch needing to be inserted with the inductance by a node splitting mode, setting 0 between the original two nodes of the branch quantity in the adjacent matrix, transferring the original branch element between the new node and one original node of the original branch, and connecting the inductance between the new node and the other original node of the original branch; (5.4) repeating step (5.3) until the number of currently inserted inductances is equal to the number of given inductances.
  6. 6. The method of deriving a common-ground converter topology according to claim 1, wherein the step (6) is specifically: If adjacent matrixes corresponding to the two topologies are identical through a renumbering mode, judging the adjacent matrixes to be isomorphic, and rejecting one of the two topologies; The feasibility screening is that when the situation that only an input source or a capacitor is directly connected with a switch in parallel or the situation that the switch and the inductor are connected in series in one branch occurs in the topology, or the situation that three inductors or two inductors and one switch respectively occur on three branches of the same node, the topology is judged to be infeasible and needs to be removed; And rejecting all the remaining topologies after the topology is rejected as legal topologies.
  7. 7. The method of deriving a common-ground converter topology according to claim 1, wherein the step (7) is specifically: (7.1) establishing a Boolean rule for each topology, and determining all legal switch working modes to obtain legal switch combinations; In a loop formed by only an input power supply, a capacitor and a switch, when the number of the switches is more than or equal to 2, all the switches cannot be conducted at the same time, and the regular Boolean expression is (S1 ∈S2 ∈S3.); in a loop formed by only an input power supply, a capacitor and a switch, when the number of the switches is more than or equal to 2, all the switches cannot be conducted at the same time, and the regular Boolean expression is ¬ (S1 ∈S2 ∈S3.); after the legal working modes of the switch are obtained, combining all legal working modes in pairs to be used as the switching logic of the converter; (7.2) traversing all loops in the topology based on depth first search DFS to obtain a loop voltage equation; For each loop, the voltage equation is obtained according to kirchhoff voltage law, and the loop equation is a loop comprising an open switch, and the loop with the switch non-conduction is not calculated; (7.3) in all loops obtained in the step (7.2), finding a unique independent loop in which each inductor is located, namely only the inductor is included in the loop, and other inductors are not included, establishing a volt-second balance equation set for each inductor by utilizing the characteristic that the integral of the inductor in the steady state is zero, combining equations of all the inductors to form a linear equation set about unknown capacitance voltage and output voltage, solving the linear equation set, and obtaining voltage gain and voltages at two ends of the capacitance; (7.4) finding out an effective loop containing each switch and energy storage element in all loops obtained in the step (7.2), substituting all known voltages obtained in the step (7.3) in the loop into kirchhoff voltage law equation, and resolving and solving the voltage expressions at two ends of the switch; (7.5) obtaining voltage gain according to the step (7.3), and judging the topology as direct current or inversion topology; (7.6) repeating the steps (7.1) - (7.5) to finish the classification judgment of all legal topologies; And (7.7) if the requirement is a direct current topology, all the inversion topologies are eliminated from all the legal topologies, and if the requirement is an inversion topology, all the direct current topologies are eliminated from all the legal topologies.

Description

Derivation method of common-ground converter topology Technical Field The invention relates to the technical field of converters, in particular to a topology deduction method of a common-ground converter. Background The non-isolated converter has wide application due to the advantages of simple structure, low cost, small energy loss and high overall efficiency. However, as no isolation exists, common-mode leakage current can be generated on the capacitance of the photovoltaic cell panel to the ground, thereby causing interference of conduction noise and harmonic current and even threatening personal safety. The expert scholars at home and abroad develop a series of effective researches on how to restrain the common-mode leakage current of the non-isolated converter, and common methods for restraining the common-mode leakage current include improving a modulation technology, adding a switching device, adding a filter, improving a control method and the like. The above method is susceptible to input power supply to ground parasitic capacitance and circuit parameter variations. In order to thoroughly eliminate the common-mode leakage current, a scholars propose a double-grounding topological structure, and the structure short-circuits the negative electrode of the direct current input and the neutral point of the alternating current output, and directly short-circuits the parasitic capacitance of the photovoltaic module to the ground, so that the common-mode leakage current is thoroughly eliminated. However, the theoretical reasoning model is complex and low in efficiency, and invalid circuits are easy to be deduced, and all circuit topologies cannot be deduced automatically through a program, so that a deducing method for deducing all common-ground converters automatically through a computer is necessary to be studied. Disclosure of Invention Aiming at the defects of the prior art, the invention provides a common-ground converter topology deriving method, which aims to solve the problem that the common-ground converter topology cannot be derived automatically through a computer, so that all the common-ground converter topologies can be derived. In order to achieve the above object, the present invention provides a method for deriving a topology of a common-ground converter, comprising the steps of: (1) Determining the node number na and the switch number nb of the common-ground converter topology, wherein the node number na and the switch number nb are at least 3 nodes and 2 switches; (2) According to the double-grounding characteristic circuit, the negative electrode of the input power supply and the negative electrode of the output end are grounded together and defined as a node 0; (3) Constructing an adjacent matrix according to the number of nodes and the number of switches, ensuring that a loop is formed between the adjacent matrix and the input power supply and the output end, and inserting switches between the nodes which are connected with each other; (4) Inserting a capacitance into the adjacency matrix, the capacitance allowing it to be placed between any two nodes; (5) Inserting an inductor into the adjacent matrix, introducing a new node into a branch needing to be inserted with the inductor in a node splitting mode, transferring an original branch element between the new node and one original node of the original branch, connecting the inductor between the new node and the other original node of the original branch, and setting 0 between the two elements of the original branch in the adjacent matrix; (6) Traversing all combinations of the steps (4) and (5) until all topologies are obtained, and carrying out isomorphic screening and feasibility screening on the obtained topologies to obtain legal topologies; (7) Based on the legal switch combination of the Boolean logic automatic enumeration legal topology, a depth-first search (DFS) traversal loop is combined, voltage gain, capacitance and voltage at two ends of the switch are calculated by utilizing a volt-second balance principle and kirchhoff voltage law, then class judgment of the topology as direct current or inversion is carried out, and the topology of the unnecessary class is removed according to the class of the requirement. Furthermore, the adjacency matrix is an N-order symmetric matrix and is used for mathematically representing the topological connection relation among all nodes in the circuit. Further, in the step (4), when capacitors are inserted into the adjacent matrix, the number of capacitors is independent of the number of nodes and the number of switches, and different capacitors can exist between two nodes at the same time. Furthermore, when a capacitor is inserted into the adjacent matrix in the step (4), if the capacitor is in an independent structure, one capacitor is connected with a parallel branch of an output load, and if the capacitor is in a grid-connected structure, the output end is directly connected with a power