CN-121997873-A - Stress simulation system and computer equipment of chip-level layout

Abstract

The invention provides a stress simulation system and computer equipment of chip-level layout, and belongs to the field of semiconductor device manufacturing. The stress management simulation system adopts a material attribute database, a simulation engine module, a thermal cycle simulation module and a virtual simulation framework of a layout configuration optimization module, thermal expansion and stress analysis of materials on a chip are simulated through the simulation engine module, initialization stress data are generated, the layout of the materials is optimally adjusted according to the initialization stress data through the layout configuration optimization module, stress accumulation in a repeated thermal cycle scene is simulated through the thermal cycle simulation module, and long-term reliability of a device is evaluated in a design stage, so that failure caused by structural problems in the later stage is avoided. The invention can optimize layout and materials at early stage to reduce defects caused by stress, reduce cost and improve the efficiency and reliability of semiconductor device design.

Inventors

• LIU FANG
• WU BO
• DENG YONGFENG
• ZHAO DONGYAN
• CHEN YINING
• HU YINGQIANG
• Mi Chaoyong
• WANG YIFAN
• ZENG MINGQUAN

Assignees

• 北京智芯微电子科技有限公司
• 浙江大学
• 国网浙江省电力有限公司电力科学研究院
• 国网浙江省电力有限公司
• 国家电网有限公司

Dates

Publication Date

20260508

Application Date

20251215

Claims (12)

1. 1. The stress simulation system of the chip-level layout is characterized by comprising a material attribute database, a simulation engine module, a thermal cycle simulation module and a layout configuration optimization module; the material attribute database is used for storing attribute parameters and layout parameters of various materials used in the chip manufacturing process; the simulation engine module is used for acquiring attribute parameters and layout parameters of the corresponding materials from the material attribute database, carrying out thermal expansion and stress analysis based on the attribute parameters and the layout parameters of the corresponding materials, generating initialization stress data, and transmitting the initialization stress data to the layout configuration optimization module; The layout configuration optimization module is used for optimizing and adjusting the layout of the material according to the initialized stress data, and returning the optimized and adjusted layout parameters to the simulation engine module; The simulation engine module is also used for performing simulation calculation according to the optimized and adjusted layout parameters, generating cyclic stress data and transmitting the cyclic stress data to the thermal cycle simulation module; The thermal cycle simulation module is used for simulating long-term stress accumulation of a chip layout in different temperature ranges or scenes of repeated thermal cycles based on the cyclic stress data.
2. 2. The system of claim 1, wherein the thermal cycle simulation module is further configured to generate cumulative damage data from the stress cycle data using a Miner linear cumulative damage theory, and to transfer the cumulative damage data to the simulation engine module.
3. 3. The system of claim 2, wherein the simulation engine module is further configured to determine whether the current cumulative damage data of the chip is within a standard range, and if so, output stress field data corresponding to the current chip-level layout.
4. 4. The system of claim 3, wherein the simulation engine module triggers the layout configuration optimization module to re-layout when determining that the current chip cumulative damage data is outside a standard range.
5. 5. The stress simulation system of a chip-scale layout of claim 3, further comprising a stress point interactive visualization module; the stress point interactive visualization module is connected with the simulation engine module and is used for displaying stress field data output by the simulation engine module in a 3D view.
6. 6. The stress simulation system of the chip-scale layout of claim 1 wherein the thermal cycle simulation module is configured with thermal cycle condition parameters including at least one of a temperature range, a number of cycles, a rate of heating and cooling.
7. 7. The system of claim 6, wherein the simulation engine module obtains thermal cycle condition parameters from the thermal cycle simulation module, performs thermal-structural coupling simulation calculations based on the optimized layout parameters and thermal cycle conditions, and generates cyclic stress data based on stress states for each cycle.
8. 8. The stress simulation system of a chip-scale layout of claim 1, wherein the simulation engine module comprises a pre-processing unit; The preprocessing unit is used for simulating thermal expansion and contraction behaviors of the material on the chip and interface stress generated by the thermal expansion and contraction by adopting a finite element analysis technology based on the attribute parameters and layout parameters of the material, and generating initialization stress data.
9. 9. The stress simulation system of a chip-scale layout of claim 8 wherein the simulation engine module comprises a solver and a post-processing unit; the solver adopts an implicit algorithm to solve nonlinear thermal-structural coupling to obtain cyclic stress data; the post-processing unit is used for extracting stress tensors, strain distribution and displacement fields from the cyclic stress data and generating stress field data and stress cyclic curves.
10. 10. The stress simulation system of the chip-scale layout according to claim 1, wherein the property parameters of the various materials stored in the material property database include at least one of thermal expansion coefficient, elastic modulus, poisson's ratio, temperature sensitive property, material-to-process association; The layout parameters include at least one of material position, material angle, material type combination, material area, and layer thickness.
11. 11. The stress simulation system of a chip level layout of claim 1 wherein the layout configuration optimization module comprises a user interaction layer and an algorithm layer; the user interaction layer comprises a visual interface, wherein the visual interface is used for adjusting the layer thickness and the area of the material and setting boundary conditions; The algorithm layer integrates an optimization algorithm, and optimizes layout parameters by using an objective function with minimum stress peak value and minimum material cost as targets.
12. 12. A computer device comprising the stress simulation system of a chip-scale layout of any of claims 1-11.

Description

Stress simulation system and computer equipment of chip-level layout Technical Field The invention relates to the field of semiconductor device manufacturing, in particular to a stress simulation system and computer equipment of chip-level layout. Background In the field of semiconductor device fabrication, and in particular BCD (bipolar-complementary metal oxide semiconductor-DMOS) processes, the design of chip-scale layout is critical to the performance and reliability of the device. The BCD process allows bipolar, complementary metal oxide semiconductor and DMOS technologies to be integrated on the same chip to achieve high performance analog and digital circuits. In BCD processes, chip-level layouts typically comprise a plurality of different materials that expand and contract at different rates under operating conditions due to different coefficients of thermal expansion. The difference in thermal expansion of the different materials results in thermally mismatched stresses that can have a severe impact on the structural integrity of the chip. To optimize thermal stress, the prior art generally performs physical testing for each layout and material combination. This approach, while capable of providing accurate stress assessment, limits its application at early design stages due to its high cost and time-consuming nature. In addition, this approach fails to predict and optimize thermal stresses early in the design phase, resulting in extended design cycles, increased development costs, and possibly significant structural problems later in the process. Disclosure of Invention In order to solve the technical defects, the invention provides a stress simulation system of a chip-level layout, which adopts an innovative virtual simulation framework, builds a simulation model aiming at the chip-level layout in a customized BCD process, manages systematic thermal mismatch stress, can identify potential stress problems in advance in a design stage, optimizes material selection and layout design, reduces dependence on physical tests, obviously shortens development period, reduces cost, and improves overall performance and reliability of products. The invention provides a stress simulation system of chip-level layout, which comprises a material attribute database, a simulation engine module, a thermal cycle simulation module and a layout configuration optimization module, wherein the material attribute database is used for storing the material attribute data; the material attribute database is used for storing attribute parameters and layout parameters of various materials used in the chip manufacturing process; the simulation engine module is used for acquiring attribute parameters and layout parameters of the corresponding materials from the material attribute database, carrying out thermal expansion and stress analysis based on the attribute parameters and the layout parameters of the corresponding materials, generating initialization stress data, and transmitting the initialization stress data to the layout configuration optimization module; The layout configuration optimization module is used for optimizing and adjusting the layout of the material according to the initialized stress data, and returning the optimized and adjusted layout parameters to the simulation engine module; The simulation engine module is also used for performing simulation calculation according to the optimized and adjusted layout parameters, generating cyclic stress data and transmitting the cyclic stress data to the thermal cycle simulation module; The thermal cycle simulation module is used for simulating long-term stress accumulation of a chip layout in different temperature ranges or scenes of repeated thermal cycles based on the cyclic stress data. In the embodiment of the invention, the thermal cycle simulation module is further used for generating accumulated damage data according to stress cycle data by adopting a Miner linear accumulated damage theory and transmitting the accumulated damage data to the simulation engine module. In the embodiment of the invention, the simulation engine module is further used for judging whether the current chip accumulated damage data is in a standard range or not, and if so, outputting stress field data corresponding to the current chip-level layout. In the embodiment of the invention, when the simulation engine module determines that the current chip accumulated damage data exceeds the standard range, the layout configuration optimization module is triggered to perform the rearrangement. In the embodiment of the invention, the system also comprises a stress point interactive visualization module; the stress point interactive visualization module is connected with the simulation engine module and is used for displaying stress field data output by the simulation engine module in a 3D view. In the embodiment of the invention, the thermal cycle simulation module is configured with thermal cycle