CN-121997874-A - Chip parasitic resistance network visualization method, electronic equipment and storage medium

CN121997874ACN 121997874 ACN121997874 ACN 121997874ACN-121997874-A

Abstract

The application discloses a visualization method of a chip parasitic resistance network, electronic equipment and a storage medium, and relates to the technical field of chips, wherein the method comprises the following steps: obtaining two-dimensional netlist data of a parasitic resistance network generated by all stacked structures of conductors in a chip according to a parasitic parameter file of the chip, obtaining a stacked structure data table of the chip according to a process parameter file of the chip, obtaining three-dimensional netlist data of the parasitic resistance network according to the stacked structure data table and the two-dimensional netlist data, establishing a first three-dimensional model of the parasitic resistance network according to the three-dimensional netlist data and establishing a second three-dimensional model of each stacked structure of the parasitic resistance network according to the process parameter file, displaying at least part of the first three-dimensional model and a target second three-dimensional model, facilitating a user to quickly search calculation problems existing in a back-end simulation calculation process based on a three-dimensional information storage table, and improving problem searching efficiency and accuracy.

Inventors

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Assignees

杭州行芯科技有限公司

Dates

Publication Date: 20260508
Application Date: 20251219

Claims (10)

1. A method for visualizing a chip parasitic resistance network, the method comprising: acquiring two-dimensional netlist data of a parasitic resistance network generated by all stacked structures of conductors in a chip according to a parasitic parameter file of the chip, wherein the two-dimensional netlist data comprises plane structure information of each parasitic resistance in the parasitic resistance network; Acquiring a stacking structure data table of the chip according to the process parameter file of the chip, wherein the stacking structure data table comprises stacking structure information of the chip; Obtaining three-dimensional netlist data of the parasitic resistance network according to the stacked structure data table and the two-dimensional netlist data, wherein the three-dimensional netlist data at least comprises three-dimensional structure information of each parasitic resistance; And establishing a first three-dimensional model of the parasitic resistance network according to the three-dimensional netlist data, establishing a second three-dimensional model of each stacked structure generating the parasitic resistance network according to the process parameter file, and displaying at least part of the first three-dimensional model and a target second three-dimensional model, wherein the target second three-dimensional model is established according to the stacked structure generating a target parasitic resistance, and the target parasitic resistance is the parasitic resistance corresponding to the displayed first three-dimensional model.
2. The method of claim 1, wherein the obtaining three-dimensional netlist data for the parasitic resistance network from the stacked structure data table and the two-dimensional netlist data comprises: Acquiring a first identifier from the two-dimensional netlist data, wherein the first identifier refers to the stacked structure of the conductor; determining stacking thickness information mapped with each first identifier from the stacking structure data table; Determining the stacking thickness information as third dimensional structure information of the parasitic resistance mapped with the first identifier in the two-dimensional netlist data; And obtaining the three-dimensional netlist data according to all the third-dimensional structure information and the two-dimensional netlist data.
3. The method of claim 2, wherein determining from the stack structure data table stack thickness information mapped to each of the first identifiers comprises: obtaining stacking thickness information mapped with a second identifier from the stacking structure data table, wherein the second identifier refers to a non-through hole type stacking structure which is a conductor; Acquiring a starting point position and an ending point position mapped with a third identifier from the stacking structure data table, wherein the third identifier refers to the stacking structure which is a through hole type and is a conductor; and calculating stacking thickness information mapped with the third identifier based on the starting point position and the ending point position of the third identifier.
4. The method of claim 1, wherein displaying at least a portion of the first three-dimensional model and the target second three-dimensional model comprises: Acquiring first selection information aiming at the parasitic resistance network, determining the parasitic resistance to be displayed in the parasitic resistance network according to the first selection information, and displaying a first three-dimensional model of the parasitic resistance to be displayed and the target second three-dimensional model in a display interface.
5. The method of claim 4, wherein displaying the first three-dimensional model of the parasitic resistance and the target second three-dimensional model to be displayed in a display interface comprises: Responding to a display mode selection operation, generating a display mode instruction, and acquiring a matched preset display mode according to the display mode instruction; according to the preset display mode which is a first display mode, the first three-dimensional model and the target second three-dimensional model which correspond to the same parasitic resistance to be displayed are displayed in a superimposed mode in the display interface; and displaying the first three-dimensional model and the target second three-dimensional model corresponding to the parasitic resistance to be displayed in a partition mode in the display interface according to the preset display mode which is the second display mode.
6. The method of claim 4, wherein the three-dimensional netlist data further includes parameter information corresponding to each of the parasitic resistances, the method further comprising: obtaining second selection information aiming at the parasitic resistance network, and obtaining and displaying matched parameter information corresponding to the parasitic resistance from the three-dimensional netlist data according to the second selection information.
7. The method of claim 1, wherein the step of creating a first three-dimensional model of the parasitic resistance network from the three-dimensional netlist data comprises: Determining three-dimensional coordinates of the parasitic resistance corresponding to each first identifier in a preset three-dimensional view according to the three-dimensional netlist node information corresponding to each first identifier in the three-dimensional netlist data, and constructing a graph of the corresponding parasitic resistance in the preset three-dimensional view according to each three-dimensional coordinate to obtain the first three-dimensional model.
8. The method according to any one of claims 1 to 7, further comprising: And acquiring an operation instruction which is input by a user and is used for adjusting the parasitic parameter file, generating a new parasitic parameter file according to the operation instruction and the adjusted simulation model, and executing the step of acquiring two-dimensional netlist data of the parasitic resistance network generated by the stacked structure of all conductors in the chip according to the parasitic parameter file of the chip again according to the new parasitic parameter file.
9. An electronic device comprising a memory and a processor, characterized in that the memory has stored therein a computer program, the processor being arranged to run the computer program to perform the method of any of claims 1 to 8.
10. A computer readable storage medium, on which a computer program is stored, characterized in that the computer program, when being executed by a processor, implements the steps of the method of any of claims 1 to 9.

Description

Chip parasitic resistance network visualization method, electronic equipment and storage medium Technical Field The present invention relates to the field of chip technologies, and in particular, to a method for visualizing a chip parasitic resistance network, an electronic device, and a storage medium. Background The Post-Layout Simulation step of designing a chip (INTEGRATED CIRCUIT, IC, also called an integrated circuit) requires performing computational simulation verification on physical characteristics of the chip at the layout level, for example, verifying whether power consumption, timing frequency, etc. of the chip meet expectations. In the simulation calculation of the power consumption and/or time sequence frequency of the chip, parasitic parameter information (parasitic resistance information, parasitic capacitance information and the like) among transistors and various interconnection wires in the chip is extracted, and a netlist is generated based on the extracted parameter information, so that the calculation problem of back-end simulation is found according to the content of the netlist. The parasitic resistance netlist in the related art is an abstract description of physical characteristics of all layer conductors of a chip, and the layer conductors of each section are abstract description into one parasitic resistance in a two-dimensional unfolding mode, so that all layer conductors are abstract into n parasitic resistances with different lengths and different resistance values, and a huge parasitic resistance network is formed by the n parasitic resistances, so that each parasitic resistance is displayed in a two-point and one-line mode in a preset two-dimensional view. However, as the integration level of the chip increases, under the condition that the contents of the parasitic resistance netlists corresponding to the wires of different layers are displayed together, complex cross overlapping may exist among different parasitic resistances in a preset two-dimensional view, so that the searching efficiency and the accuracy of the user for searching the simulation calculation problem based on the parasitic resistance netlists of the related technology are low. Disclosure of Invention The application provides a visualization method, electronic equipment and storage medium of a chip parasitic resistance network, and aims to solve the problems of low efficiency and low accuracy of parasitic resistance netlist file searching simulation calculation in the related technology. To achieve the above object: in a first aspect, an embodiment of the present application provides a method for visualizing a chip parasitic resistance network, the method including: acquiring two-dimensional netlist data of a parasitic resistance network generated by all stacked structures of conductors in a chip according to a parasitic parameter file of the chip, wherein the two-dimensional netlist data comprises plane structure information of each parasitic resistance in the parasitic resistance network; Acquiring a stacking structure data table of the chip according to the process parameter file of the chip, wherein the stacking structure data table comprises stacking structure information of the chip; Obtaining three-dimensional netlist data of the parasitic resistance network according to the stacked structure data table and the two-dimensional netlist data, wherein the three-dimensional netlist data at least comprises three-dimensional structure information of each parasitic resistance; And establishing a first three-dimensional model of the parasitic resistance network according to the three-dimensional netlist data, establishing a second three-dimensional model of each stacked structure generating the parasitic resistance network according to the process parameter file, and displaying at least part of the first three-dimensional model and a target second three-dimensional model, wherein the target second three-dimensional model is established according to the stacked structure generating a target parasitic resistance, and the target parasitic resistance is the parasitic resistance corresponding to the displayed first three-dimensional model. In an embodiment, the obtaining the three-dimensional netlist data of the parasitic resistance network according to the stacked structure data table and the two-dimensional netlist data includes: Acquiring a first identifier from the two-dimensional netlist data, wherein the first identifier refers to the stacked structure of the conductor; determining stacking thickness information mapped with each first identifier from the stacking structure data table; Determining the stacking thickness information as third dimensional structure information of the parasitic resistance mapped with the first identifier in the two-dimensional netlist data; And obtaining the three-dimensional netlist data according to all the third-dimensional structure information and the two-dimensional netl