CN-121997876-A - Method, apparatus, computer device, readable storage medium, and program product for generating chip product

Abstract

The present application relates to a method, an apparatus, a computer device, a readable storage medium and a program product for generating a chip product. The method comprises the steps of processing an initial functional netlist and chip design data based on an interconnection logic generation strategy to obtain a target functional netlist of a chip to be generated, determining a target physical layout generation strategy based on a layout generation algorithm, the target functional netlist and the chip design data, virtually assembling the chip to be generated in a virtual assembly module based on the target functional netlist and the target physical layout generation strategy to obtain an initial system level layout, checking the initial system level layout based on a checking strategy to obtain a checking result, and outputting physical design data corresponding to the system level layout meeting a checking completion condition if the checking result meets a preset checking completion condition. The method can improve the manufacturing efficiency of the chip product.

Inventors

• XU YUE
• LIU YANG
• LIU YANGFAN
• TANG WEI

Assignees

• 上海灵睿智芯计算技术有限公司

Dates

Publication Date

20260508

Application Date

20260115

Claims (10)

1. 1. A method of generating a chip product, the method comprising: Processing the initial functional netlist and the chip design data based on an interconnection logic generation strategy to obtain a target functional netlist of the chip to be generated; determining a target physical layout generation strategy based on a layout generation algorithm, the target functional netlist and the chip design data; In the virtual assembly module, virtual assembly is carried out on the chip to be generated based on the target functional netlist and the target physical layout generation strategy to obtain an initial system level layout, verification is carried out on the initial system level layout based on the verification strategy to obtain a verification result, and if the verification result meets a preset verification completion condition, physical design data corresponding to the system level layout meeting the verification completion condition is output.
2. 2. The method of claim 1, wherein the processing the initial functional netlist and the chip design data based on the interconnect logic generation strategy to obtain a target functional netlist of the chip to be generated comprises: determining each to-be-processed interconnection interface of the chip to be generated based on chip design data; Performing redundancy processing on each to-be-processed interconnection interface which does not meet the activation conditions based on a redundancy processing strategy to obtain each redundancy interface; Carrying out instantiation processing on each activated interconnection interface based on a preset IP library to obtain each instantiation interconnection module; And updating the initial functional netlist based on each instantiation interconnection module and each redundant interface, and determining the target functional netlist of the chip to be generated.
3. 3. The method of claim 2, wherein the chip design data includes at least physical layout data for a chip to be generated, wherein the determining a target physical layout generation strategy based on a layout generation algorithm, the target functional netlist and the chip design data comprises: Generating position constraint strategies corresponding to the instantiation interconnection modules in the target functional netlist respectively based on the physical layout data, determining interconnection links between chips to be generated based on the target functional netlist, determining interconnection wiring channel constraint strategies of the interconnection links based on the chip design data, and determining time sequence constraint strategies of the interconnection links based on interconnection channel delay thresholds; And determining a target physical layout generation strategy based on the position constraint strategy, the interconnection wiring channel constraint strategy and the time sequence constraint strategy.
4. 4. The method of claim 3, wherein the determining a target physical layout generation policy based on the location constraint policy, the interconnect routing channel constraint policy, and the timing constraint policy comprises: If the interconnection wiring channel constraint strategy does not meet the screening condition, optimizing the interconnection wiring channel constraint strategy to obtain an interconnection wiring channel optimization strategy; if the time sequence constraint strategy does not meet the screening condition, optimizing the time sequence constraint strategy to obtain a time sequence optimization strategy; And determining a target physical layout generation strategy based on the position constraint strategy, the interconnection wiring channel optimization strategy and the time sequence optimization strategy.
5. 5. The method according to claim 1, wherein the verification result includes a size comparison result and a signal verification result, and the verifying the initial system level layout based on the verification policy to obtain a verification result includes: Determining the size of a bounding box of the initial system level layout, and comparing the size of the bounding box with a preset size threshold value to obtain the size comparison result; and verifying the time sequence information and the signal integrity information of the initial system level layout based on a systematic verification strategy to obtain the signal verification result.
6. 6. The method of claim 5, wherein the method further comprises: If the size comparison result is that the size of the bounding box is larger than or equal to the preset size threshold value, and/or if the time sequence information exceeds a preset time sequence range and the signal integrity information does not meet a preset integrity condition, determining that the verification result does not meet the preset verification completion condition, determining deviation data of the initial system level layout, and generating a target optimization strategy corresponding to the deviation data in a corresponding relation between the deviation data and the optimization strategy; Correcting the target physical layout generation strategy based on the target optimization strategy to obtain a corrected physical layout generation strategy, continuously executing the steps in the virtual assembly module based on the target functional netlist and the target physical layout generation strategy, virtually assembling the chip to be generated to obtain an initial system level layout until the verification result meets the verification completion condition.
7. 7. A chip product generating apparatus, the apparatus comprising: the processing module is used for processing the initial functional netlist and the chip design data based on the interconnection logic generation strategy to obtain a target functional netlist of the chip to be generated; The determining module is used for determining a target physical layout generating strategy based on a layout generating algorithm, the target functional netlist and the chip design data; The verification module is used for virtually assembling the chip to be generated based on the target functional netlist and the target physical layout generation strategy in the virtual assembly module to obtain an initial system level layout, verifying the initial system level layout based on the verification strategy to obtain a verification result, and outputting physical design data corresponding to the system level layout meeting the verification completion condition if the verification result meets the preset verification completion condition.
8. 8. A computer device comprising a memory and a processor, the memory storing a computer program, characterized in that the processor implements the steps of the method of any of claims 1 to 6 when the computer program is executed.
9. 9. A computer readable storage medium, on which a computer program is stored, characterized in that the computer program, when being executed by a processor, implements the steps of the method of any of claims 1 to 6.
10. 10. A computer program product comprising a computer program, characterized in that the computer program, when being executed by a processor, implements the steps of the method of any of claims 1 to 6.

Description

Method, apparatus, computer device, readable storage medium, and program product for generating chip product Technical Field The present application relates to the field of integrated circuit design and manufacturing technology, and in particular, to a method, an apparatus, a computer device, a readable storage medium, and a program product for generating a chip product. Background With the continuous development of semiconductor technology, the physical limit is continuously approached, and a single large-size chip faces the problem of complex design. In this context, multi-chip integration technology, particularly wafer level integrated interconnect (ICI) technology, has become an important development in the industry to interconnect multiple smaller dies (or die Chiplet) in a high density on a planar surface to build larger scale computing systems. In the related art, single chips (Monolithic Die) with different functions or scales are designed for different target markets (such as middle-end and high-end), and dedicated chip versions with different physical layout and interconnection interfaces are designed for the scene of multi-chip integration. These different versions of the chip need to undergo independent and complete design, verification, and flow processes, resulting in less efficient development and manufacturing of the chip product. Disclosure of Invention In view of the foregoing, it is desirable to provide a method, an apparatus, a computer device, a readable storage medium, and a program product for generating a chip product that can improve the development and manufacturing efficiency of the chip product. In a first aspect, the present application provides a method for generating a chip product, including: Processing the initial functional netlist and the chip design data based on an interconnection logic generation strategy to obtain a target functional netlist of the chip to be generated; determining a target physical layout generation strategy based on a layout generation algorithm, the target functional netlist and the chip design data; In the virtual assembly module, virtual assembly is carried out on the chip to be generated based on the target functional netlist and the target physical layout generation strategy to obtain an initial system level layout, verification is carried out on the initial system level layout based on the verification strategy to obtain a verification result, and if the verification result meets a preset verification completion condition, physical design data corresponding to the system level layout meeting the verification completion condition is output. In one embodiment, the processing the initial functional netlist and the chip design data based on the interconnection logic generation strategy to obtain a target functional netlist of the chip to be generated includes: determining each to-be-processed interconnection interface of the chip to be generated based on chip design data; Performing redundancy processing on each to-be-processed interconnection interface which does not meet the activation conditions based on a redundancy processing strategy to obtain each redundancy interface; Carrying out instantiation processing on each activated interconnection interface based on a preset IP library to obtain each instantiation interconnection module; And updating the initial functional netlist based on each instantiation interconnection module and each redundant interface, and determining the target functional netlist of the chip to be generated. In one embodiment, the chip design data at least comprises physical layout data of a chip to be generated, and the determining a target physical layout generation strategy based on a layout generation algorithm, the target functional netlist and the chip design data comprises: Generating position constraint strategies corresponding to the instantiation interconnection modules in the target functional netlist respectively based on the physical layout data, determining interconnection links between chips to be generated based on the target functional netlist, determining interconnection wiring channel constraint strategies of the interconnection links based on the chip design data, and determining time sequence constraint strategies of the interconnection links based on interconnection channel delay thresholds; And determining a target physical layout generation strategy based on the position constraint strategy, the interconnection wiring channel constraint strategy and the time sequence constraint strategy. In one embodiment, the determining the target physical layout generation policy based on the location constraint policy, the interconnect routing channel constraint policy, and the timing constraint policy includes: If the interconnection wiring channel constraint strategy does not meet the screening condition, optimizing the interconnection wiring channel constraint strategy to obtain an interconnection wiring chann