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CN-121997877-A - Signal quality optimization method, device and medium

CN121997877ACN 121997877 ACN121997877 ACN 121997877ACN-121997877-A

Abstract

The invention discloses a signal quality optimization method, a device and a medium, relates to the technical field of circuit design, and provides a signal quality optimization method aiming at the problem that a reflow path cannot be improved through ground vias in a packaging dense area such as BGA (ball grid array). Capacitance is added at the power vias to connect to the ground plane. The signal return path can directly reach the ground plane through the power supply via hole and the capacitor, so that the signal return path is shortened, the integrity of the signal impedance is improved, and the signal quality is improved. The capacitor is buried in a grounding layer below a power layer where the power via hole is located, the power via hole penetrates to the grounding layer through a blind hole to be connected with a first end of the capacitor, a second end of the capacitor is connected with the grounding hole, and the grounding hole is a via hole penetrating from the grounding layer to the bottom layer of the printed circuit board. Based on the arrangement, the embedded capacitor does not occupy an effective surface layer and a signal layer, and the signal pins below the ground layer can be used as a return path by referring to the ground holes, so that the signal quality is further optimized.

Inventors

  • LI NAN
  • RONG SHILI
  • LI WEI

Assignees

  • 浪潮计算机科技有限公司

Dates

Publication Date
20260508
Application Date
20260129

Claims (10)

  1. 1. A method for optimizing signal quality, comprising: Positioning signal pins in a printed circuit board, which need to improve signal quality, and determining power supply pins around the signal pins as target pins; Leading out a power via hole corresponding to the target pin on the surface layer of the printed circuit board, and penetrating the power via hole to a grounding layer below a power layer where the power pin is positioned through a blind hole; embedding a capacitor in the ground layer, wherein a first end of the capacitor is connected with the power supply via hole; And a ground hole from the ground layer to the bottom layer is opened, and the second end of the capacitor is connected with the ground hole.
  2. 2. The method of claim 1, wherein the capacitor is a decoupling capacitor of the power pin.
  3. 3. The signal quality optimization method according to claim 1 or 2, wherein the number of the capacitors is plural, and each of the capacitors is connected in parallel.
  4. 4. The signal quality optimization method of claim 3, wherein the capacitance value of each capacitor is different, and the capacitance value of each capacitor is determined according to the frequency of the power supply noise corresponding to the power supply pin.
  5. 5. The signal quality optimization method of claim 1, wherein a distance between the first end of the capacitor and the power via and a distance between the second end of the capacitor and the ground hole are each less than 0.5mm.
  6. 6. The signal quality optimization method of claim 1, wherein a width of the trace between the first end of the capacitor and the power via and the trace between the second end of the capacitor and the ground via is greater than or equal to 0.2mm.
  7. 7. The method of claim 1, wherein the routing between the first end of the capacitor and the power via and the routing between the second end of the capacitor and the ground via are straight line segments or a combination of straight line segments and 45 ° angular fold segments or circular arc segments.
  8. 8. A signal quality optimization apparatus, comprising: The positioning module is used for positioning signal pins needing to improve signal quality in the printed circuit board and determining power supply pins around the signal pins as target pins; The via hole module is used for leading out a power supply via hole corresponding to the target pin from the surface layer of the printed circuit board and enabling the power supply via hole to penetrate to a grounding layer below a power supply layer where the power supply pin is positioned through the blind hole; The capacitor burying module is used for burying a capacitor in the grounding layer, and the first end of the capacitor is connected with the power supply via hole; and the grounding module is used for opening a grounding hole from the grounding layer to the bottom layer, and the second end of the capacitor is connected with the grounding hole.
  9. 9. A signal quality optimization apparatus, comprising: A memory for storing a computer program; Processor for implementing the steps of the signal quality optimization method according to any of claims 1 to 7 when executing said computer program.
  10. 10. A non-volatile storage medium, characterized in that it has stored thereon a computer program which, when executed by a processor, implements the steps of the signal quality optimization method according to any of claims 1 to 7.

Description

Signal quality optimization method, device and medium Technical Field The present invention relates to the field of circuit design technologies, and in particular, to a method, an apparatus, and a medium for optimizing signal quality. Background In high-speed circuit designs, the return path of the signal has a critical impact on signal quality. Typically, the optimal return path for the signal is Ground (GND). For traces it is desirable to be able to refer to the GND plane to ensure stability of signal transmission, for signal pins (pins) it is desirable that GND pins accompany to provide good return paths, for high speed signal fanout vias in the Ball Grid Array (BGA) area it is desirable that they be surrounded by adjacent ground vias (via) to reduce signal reflection and cross talk. However, in practical circuit designs, some unavoidable conditions are often encountered. For example, in a BGA area, multiple power pins may be distributed around the high-speed differential signal pins without space for vias. And these power pins cannot be replaced with GND pins due to design constraints or other reasons, it is difficult to improve the return path directly through the ground vias. Such an arrangement may cause the return path of the high-speed signal to be disturbed and the signal quality to be degraded. The method is characterized in that the impedance curve of the differential via hole is oscillated, the return loss is increased and the like, so that the performance and the reliability of the whole circuit system are affected. Therefore, a signal quality optimization method is needed by those skilled in the art to solve the problem that the reflow path cannot be improved by the ground vias in the densely packed area such as BGA. Disclosure of Invention The invention aims to provide a signal quality optimization method, a device and a medium, which are used for solving the problem that a reflow path cannot be improved through ground vias in a packaging dense area such as BGA (ball grid array). In order to solve the above technical problems, the present invention provides a signal quality optimization method, including: Positioning signal pins in a printed circuit board, which need to improve signal quality, and determining power supply pins around the signal pins as target pins; Leading out a power via hole corresponding to the target pin on the surface layer of the printed circuit board, and penetrating the power via hole to a grounding layer below a power layer where the power pin is positioned through a blind hole; embedding a capacitor in the ground layer, wherein a first end of the capacitor is connected with the power supply via hole; And a ground hole from the ground layer to the bottom layer is opened, and the second end of the capacitor is connected with the ground hole. In an alternative embodiment, the capacitor is a decoupling capacitor of the power pin. In an alternative embodiment, the number of the capacitors is a plurality, and each capacitor is connected in parallel. In an alternative embodiment, the capacitance value of each capacitor is different, and the capacitance value of each capacitor is determined according to the frequency of the power supply noise corresponding to the power supply pin. In an alternative embodiment, the distance between the first end of the capacitor and the power via and the distance between the second end of the capacitor and the ground hole are both less than 0.5mm. In an alternative embodiment, the width of the trace between the first end of the capacitor and the power via and the trace between the second end of the capacitor and the ground via is greater than or equal to 0.2mm. In an alternative embodiment, the routing between the first end of the capacitor and the power via and the routing between the second end of the capacitor and the ground via are straight line segments, or a combination of straight line segments and 45 ° angular fold segments or circular arc segments. In order to solve the above technical problem, the present invention further provides a signal quality optimization device, including: The positioning module is used for positioning signal pins needing to improve signal quality in the printed circuit board and determining power supply pins around the signal pins as target pins; The via hole module is used for leading out a power supply via hole corresponding to the target pin from the surface layer of the printed circuit board and enabling the power supply via hole to penetrate to a grounding layer below a power supply layer where the power supply pin is positioned through the blind hole; The capacitor burying module is used for burying a capacitor in the grounding layer, and the first end of the capacitor is connected with the power supply via hole; and the grounding module is used for opening a grounding hole from the grounding layer to the bottom layer, and the second end of the capacitor is connected with the grounding hole. In order