CN-121997879-A - Device layout method and device of high acceleration stress test carrier plate and electronic equipment

CN121997879ACN 121997879 ACN121997879 ACN 121997879ACN-121997879-A

Abstract

The application relates to the technical field of integrated circuit packaging, and provides a device layout method and device of a high-acceleration stress test carrier plate and electronic equipment. The method comprises the steps of determining a device to be laid out corresponding to each target pin line of a chip to be tested, determining initial coordinates of the corresponding device to be laid out based on end point coordinates of the target pin lines, grouping each device to be laid out based on the initial coordinates of each device to be laid out to obtain grouping information corresponding to each device to be laid out, performing offset adjustment on the initial coordinates corresponding to each device to be laid out based on the grouping information corresponding to each device to be laid out to obtain target layout coordinates of each device to be laid out, and enabling the devices to be laid out which are densely distributed or even projected to overlap in a local area originally through progressive adjustment of grouping and offset.

Inventors

WU QIYIN
ZENG LUJUN
NI WEIHUA

Assignees

江山季丰电子科技有限公司

Dates

Publication Date: 20260508
Application Date: 20260408

Claims (10)

1. A device layout method for a high acceleration stress test carrier, the method comprising: Determining a device to be laid out corresponding to each target pin line of a chip to be tested, and determining initial coordinates of the corresponding device to be laid out based on end point coordinates of the target pin lines; Grouping each device to be laid out based on the initial coordinates of each device to be laid out to obtain grouping information corresponding to each device to be laid out; and carrying out offset adjustment on the initial coordinates corresponding to each device to be laid out based on the grouping information corresponding to each device to be laid out, so as to obtain the target layout coordinates of each device to be laid out.
2. The method according to claim 1, wherein grouping each device to be laid out based on the initial coordinates of each device to be laid out to obtain grouping information corresponding to each device to be laid out comprises: traversing all initial coordinates of the devices to be laid out, and acquiring a first coordinate grouping value corresponding to a first direction on a vertical axis, a second coordinate grouping value corresponding to a second direction on the vertical axis, a third coordinate grouping value corresponding to a third direction on a horizontal axis and a fourth coordinate grouping value corresponding to a fourth direction on the horizontal axis, wherein the first direction and the second direction are opposite directions, and the third direction and the fourth direction are opposite directions; And respectively matching the initial coordinates of each device to be laid out with the first coordinate grouping value, the second coordinate grouping value, the third coordinate grouping value and the fourth coordinate grouping value, and determining grouping information of each device to be laid out according to a matching result.
3. The method according to claim 2, wherein determining grouping information of each of the devices to be laid out according to the matching result comprises: If the matching result represents that the initial coordinates of the devices to be laid out are matched with the first coordinate grouping values, determining that grouping information of the devices to be laid out is vertical axis first grouping; And if the matching result represents that the initial coordinates of the devices to be laid out are matched with the second coordinate grouping values, determining that the grouping information of the devices to be laid out is a vertical axis second grouping.
4. A method according to any one of claims 1 to 3, wherein performing offset adjustment on initial coordinates corresponding to each device to be laid out based on the grouping information corresponding to each device to be laid out to obtain target layout coordinates of each device to be laid out, includes: Sequencing the devices to be laid out with the same grouping information to obtain a sequencing result; Acquiring a preset device interval and a first offset axis corresponding to each piece of grouping information; And performing offset adjustment on the initial coordinates of the devices to be laid out under each piece of grouping information according to the first offset axis, the device spacing and the sequencing result corresponding to each piece of grouping information to obtain target layout coordinates of each device to be laid out.
5. The method of claim 4, wherein performing offset adjustment on the initial coordinates of the devices to be laid out under each group information according to the first offset axis, the device pitch and the sorting result corresponding to each group information to obtain target layout coordinates of each device to be laid out, comprises: determining the intra-group relative displacement of each device to be laid out based on the product of the serial index of each device to be laid out in the sequencing result and the device spacing; And accumulating the coordinate component corresponding to the first offset axis in the initial coordinates of each device to be laid out with the relative displacement in the group to determine the target layout coordinates of each device to be laid out.
6. The method of claim 5, wherein accumulating the coordinate component of each of the initial coordinates of the devices to be laid out corresponding to the first offset axis with the relative displacement in the group to determine the target layout coordinates of each of the devices to be laid out, comprising: accumulating the coordinate component corresponding to the first offset axis in the initial coordinate of each device to be laid out with the relative displacement in the group to obtain an intermediate layout coordinate; Acquiring the level information of the target pin lines corresponding to each device to be laid out, and determining the level relative displacement of each device to be laid out according to the level information and the preset level interval; and accumulating the coordinate component corresponding to the second offset axis in the middle layout coordinates of each device to be laid out and the relative displacement of the hierarchy to obtain the target layout coordinates of each device to be laid out, wherein the second offset axis and the first offset axis are different coordinate axes.
7. A method according to any one of claims 1-3, wherein the method further comprises: Determining a routing path between each device to be laid out and the corresponding target pin line based on the target layout coordinates of each device to be laid out and the end point coordinates of the target pin line of each device to be laid out; and generating an electric connection line for connecting the device to be laid out and the corresponding target pin line according to the wiring path.
8. A device layout apparatus for a high acceleration stress test carrier, the apparatus comprising: The coordinate module is used for determining a device to be laid out corresponding to each target pin line of the chip to be tested, and determining the initial coordinate of the corresponding device to be laid out based on the terminal point coordinate of the target pin line; The grouping module is used for grouping each device to be laid out based on the initial coordinates of each device to be laid out to obtain grouping information corresponding to each device to be laid out; And the adjustment module is used for carrying out offset adjustment on the initial coordinates corresponding to each device to be laid out based on the grouping information corresponding to each device to be laid out so as to obtain the target layout coordinates of each device to be laid out.
9. An electronic device comprising a memory, a processor and a computer program stored in the memory and executable on the processor, characterized in that the processor implements the steps of the method according to any of claims 1 to 7 when the computer program is executed.
10. A computer readable storage medium storing a computer program, characterized in that the computer program when executed by a processor implements the steps of the method according to any one of claims 1 to 7.

Description

Device layout method and device of high acceleration stress test carrier plate and electronic equipment Technical Field The present application relates to the field of integrated circuit packaging technology, and in particular, to a device layout method and apparatus for a high acceleration stress test carrier, and an electronic device. Background With the rapid development of integrated circuit packaging technology, the pin density of Ball grid array (Ball GRID ARRAY, BGA) chips is increasing, especially in the design of high-density test carrier boards such as highly accelerated stress test (HIGHLY ACCELERATED STRESS TEST, HAST) and Burn-in (Burn-in test), a large number of bias resistors or decoupling capacitors are required to be distributed on the periphery of the chips, so as to provide stable pin bias for HAST test. In existing PCB design flows, the layout of such devices is largely dependent on manual processing, since the chip to be tested typically has hundreds or even thousands of pins. The designer needs to identify the pin network names one by one, find the corresponding schematic diagram device, and manually move the resistors to the corresponding pin outlet ends. In the face of a large pin base, manual placement is extremely time consuming and is highly prone to misalignment or omission. Disclosure of Invention In view of the above, the embodiments of the present application provide a device layout method and apparatus for a high acceleration stress test carrier, and an electronic device, so as to solve the problems of time consumption and easy error caused by manually performing the device layout of the high acceleration stress test carrier in the prior art. The device layout method of the high acceleration stress test carrier plate comprises the steps of determining devices to be laid corresponding to each target pin line of a chip to be tested, determining initial coordinates of the corresponding devices to be laid based on end point coordinates of the target pin lines, grouping the devices to be laid based on the initial coordinates of the devices to be laid to obtain grouping information corresponding to the devices to be laid, and performing offset adjustment on the initial coordinates corresponding to the devices to be laid based on the grouping information corresponding to the devices to be laid to obtain target layout coordinates of the devices to be laid. The device layout device of the high acceleration stress test carrier plate comprises a coordinate module, a grouping module and an adjusting module, wherein the coordinate module is used for determining devices to be laid corresponding to each target pin line of a chip to be tested, determining initial coordinates of the corresponding devices to be laid based on end point coordinates of the target pin line, grouping the devices to be laid based on the initial coordinates of the devices to be laid to obtain grouping information corresponding to the devices to be laid, and the adjusting module is used for performing offset adjustment on the initial coordinates corresponding to the devices to be laid based on the grouping information corresponding to the devices to be laid to obtain target layout coordinates of the devices to be laid. In a third aspect of the embodiments of the present application, there is provided an electronic device comprising a memory, a processor and a computer program stored in the memory and executable on the processor, the processor implementing the steps of the above method when executing the computer program. In a fourth aspect of the embodiments of the present application, there is provided a computer readable storage medium storing a computer program which, when executed by a processor, implements the steps of the above method. Compared with the prior art, the method for testing the device layout of the carrier board with the high acceleration stress has the advantages that the device layout method of the carrier board with the high acceleration stress determines the device to be laid corresponding to each target pin line, determines the initial coordinates of the corresponding device to be laid based on the end point coordinates of the target pin line, groups each device to be laid based on the initial coordinates of each device to be laid to obtain grouping information corresponding to each device to be laid, and performs offset adjustment on the initial coordinates corresponding to each device to be laid based on the grouping information corresponding to each device to be laid to obtain the target layout coordinates of each device to be laid. The problems of time consumption and easy error caused by manually carrying out the device layout of the high-acceleration stress test carrier plate in the related technology are avoided. Drawings In order to more clearly illustrate the technical solutions of the embodiments of the present application, the drawings used in the embodiments or the description of th