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CN-121997881-A - Chiplet-oriented automatic wiring method

CN121997881ACN 121997881 ACN121997881 ACN 121997881ACN-121997881-A

Abstract

The invention discloses an automatic wiring method for Chiplet, which comprises the steps of S1, preprocessing, obtaining Chiplet wiring data, splitting a multi-terminal wire net into two-terminal wire nets, carrying out via planning and end point distribution of an FA wire net, and constructing global wiring map resources by utilizing a Voronoi grid, S2, carrying out Inter-Chip wire net planning, grouping, layer distribution, escape line sequence planning, escape point determination and punching area and wiring area division on the Inter-Chip wire net, selecting an optimal fan-out mode for each wire net to determine via positions, S3, carrying out 3D-A routing, and carrying out wire routing by using a 3D-A algorithm with cross perception based on the global wiring map resources and planning results. The invention realizes the global wiring function in the 2.5D Chiplet package and can effectively improve the wiring efficiency and the wiring quality in the detailed wiring.

Inventors

  • XU NING
  • ZHU ZHANYANG

Assignees

  • 武汉理工大学

Dates

Publication Date
20260508
Application Date
20260115

Claims (10)

  1. 1. A Chiplet-oriented automatic wiring method, the method comprising: step S1, preprocessing, namely acquiring Chiplet wiring data, splitting a multi-terminal wire network into two-terminal wire networks, carrying out via planning and end point distribution of an FA wire network, and constructing global wiring map resources by utilizing Voronoi grids; step S2, performing grouping, layer distribution, escape line sequence planning, escape point determination and perforation area and wiring area division on the Inter-Chip network, and selecting an optimal fan-out mode for each network to determine via holes; And step S3, 3D-A routing, wherein the routing is performed by using a 3D-A algorithm with cross perception based on global wiring map resources and planning results.
  2. 2. The automatic Chiplet-oriented routing method of claim 1, wherein the via programming comprises: (1) Pre-processing via hole planning; For the PA wire mesh, a via hole is arranged at the position corresponding to the I/O pad and the bump pad in each redistribution layer; For the FA network, the bump pad positions of the FA network are optimized by using a simulated annealing algorithm SA to convert the FA network into the PA network, and through holes are arranged at positions corresponding to the I/O pads and the bump pads in each layer of redistribution layer, wherein the optimization targets of the simulated annealing algorithm SA comprise the crossing number of flying wires and the wire length of the flying wires; (2) Performing final treatment on the via hole planning; Equally dividing the wiring map into areas with the same size; Projecting the information of the I/O pads, the Bump pads and the through holes of the upper layer and the information of the C4 Bump layer to the current redistribution layer, and generating a new through hole in the center of the area if the number of the pads in the projected area is smaller than a preset number value; after the global routing is completed, unused vias are deleted.
  3. 3. The Chiplet-oriented automatic routing method of claim 2, wherein an initial solution of an annealing algorithm SA is simulated Selecting the latest bump pad for the I/O pads in the FA network to be matched with; The perturbation rule includes exchanging the bump pads of two FA nets and reselecting an unselected bump pad for the FA net.
  4. 4. The Chiplet-oriented automatic routing method of claim 1, wherein building a global routing map resource using a Voronoi mesh comprises: Identifying an escape area and a non-escape area in a wiring area, wherein a regular quadrilateral grid is used in the escape area, and a Voronoi grid is used in the non-escape area; Constructing wiring nodes at the middle point of each Voronoi side and the positions of the via holes according to the via hole planning result, setting the capacity of the wiring nodes at the middle point of the Voronoi sides according to the length of the Voronoi sides and the line width and line spacing of the wiring, wherein the capacity of the via hole wiring nodes is 1; When each wiring passes through the wiring node of the midpoint of the Voronoi side, two new wiring nodes are generated on two sides according to the line width and the line interval of the wiring, for the wiring node of the Voronoi side which is not the midpoint, the new wiring node is generated on one side of the wiring node, and the capacity which is not more than the set capacity is ensured when the new wiring node is generated.
  5. 5. The Chiplet-oriented automatic routing method of claim 1, wherein grouping comprises: Obtaining netlist information after wire mesh splitting and wire mesh classification, and dividing an Inter-Chip wire mesh into a plurality of groups according to connection relations among different devices, namely splitting the Inter-Chip wire mesh into sub-models which are mutually connected in pairs according to the groups; for each sub-model, dividing the sub-models into a plurality of subgroups according to the physical positions of the bonding pads; The layer allocation includes: for each subgroup, determining an escape boundary and boundary capacity, and distributing the bonding pads of each subgroup to different redistribution layers according to the boundary capacity, wherein if the escape boundary is enough for all bonding pads in the subgroup to escape, only one redistribution layer is used for distributing all bonding pads in the subgroup, otherwise, all bonding pads in the subgroup are divided into a plurality of parts from left to right, and each part corresponds to one redistribution layer; escape route planning includes: Dividing all bonding pads of each group in each layer of redistribution layer into an upper part and a lower part, wherein the sequence of the bonding pads of the upper part is arranged in front, the sequence of the bonding pads of the lower part is arranged in back, the upper part and the lower part respectively form a topological disc, and the distributed line sequences are unfolded at two sides of an escape point and are identical in sequence, so that the simultaneous escape wiring is changed into an orderly escape wiring, and the escape sequence on an escape boundary is obtained; the escape point determination includes: after the escape sequence is determined, the sequence is gradually unfolded from left to right to the escape boundary, the bonding pads of the upper half part are unfolded from top to bottom, and the bonding pads of the lower half part are unfolded from bottom to top to determine each escape point.
  6. 6. The automatic routing method for Chiplet of claim 1, wherein the perforating area and routing area partitioning comprises: dividing the area of each redistribution layer into a punching area, a wiring punching area and a blank area, wherein the punching area is a through hole area of an upper redistribution layer reserved by a wire net of a next redistribution layer, the wiring punching area is an area with holes and wires, and the blank area is not punched and not wired, and is specific: Each redistribution layer sequentially comprises a wire mesh of the lowest redistribution layer which is left in a via area of the current redistribution layer until a wire mesh of a next redistribution layer of the current redistribution layer is left in the via area, a wiring punching area and a blank area of the current redistribution layer, wherein the blank area does not exist in the first redistribution layer, and the punching area does not exist in the lowest redistribution layer.
  7. 7. The automatic Chiplet-oriented routing method of claim 6, wherein selecting an optimal fan-out pattern for each net to determine via locations comprises: four fan-out directions are arranged on each bonding pad, three fan-out modes are arranged in each fan-out direction, and 12 fan-out modes are arranged on each bonding pad in total; And selecting an optimal fan-out mode for each bonding pad according to an evaluation index and finally determining a punching position, wherein the evaluation index comprises whether the fan-out mode is positioned in a punching area, whether conflict exists between the fan-out mode and other wire meshes in an RDL layer or not and whether the wire length exists in the RDL layer or not.
  8. 8. The automatic wiring method facing Chiplet according to claim 1, wherein step S3 includes: and for each Voronoi grid, generating a disc model to judge whether the wires are crossed so as to realize the crossed sensing, and calculating the congestion degree so as to evaluate the congestion degree.
  9. 9. A computer apparatus/device/system comprising a memory, a processor and a computer program stored on the memory, characterized in that the processor executes the computer program to implement the steps of the method of any one of claims 1 to 8.
  10. 10. A computer readable storage medium having stored thereon a computer program/instruction, which when executed by a processor, implements the steps of the method of any of claims 1 to 8.

Description

Chiplet-oriented automatic wiring method Technical Field The invention relates to the field of electronic design automation, in particular to an automatic wiring method oriented to Chiplet. Background With the demands of higher integration density, good electrical performance, smaller time sequence delay, shorter vertical interconnection and the like of chips, semiconductor products are developed from two dimensions to three dimensions, and advanced packaging technologies such as Flip-Chip (Flip-Chip), 2.5D packaging and the like are developed in the technology implementation method. They not only provide powerful support for performance enhancement, power consumption reduction, and volume reduction of integrated circuits, but also play a key role in pushing electronic products toward higher integration, smaller size, and lower cost. In 2.5D package routing, the redistribution layer (redistribution layer, RDL) plays a critical role. Inside the package, RDLs are used to complete the connection between Input/Output (I/O) pads and bottom Bump (Bump) pads. FIG. 1 shows the structure of a multi-chip, multi-layer RDL package. Under multiple chips, there are multiple RDLs to redistribute signal connections. These RDLs consist of alternating stacked via layers and wiring layers, with the top RDL connected to the I/O pads and the bottom RDL connected to the bottom C4 Bump pads. 2.5D package routing can be understood as routing on RDL, and RDL routing problems can be categorized into three types, (1) Free-Assignment (FA Net) routing, (2) Pre-Assignment (PA Net) routing, and (3) Inter-die escape (Int-Chip Net) routing. In Free-Assignment net routing, the router can freely connect a net between any one I/O Pad and any one Bump Pad. In the Pre-Assignment net wiring, the net connection between the I/O Pad and the Bump Pad is predefined before wiring. In the Inter-Chip net wiring, nets are defined in two die, respectively. The wiring scenario and problems for a multi-chip, multi-layer RDL layer 2.5D package wiring are complex and the number of wiring nets is extremely large. Because of the dramatic increase in the wiring scale, it is necessary to split the wiring problem into global wiring that provides a wiring guide to the detailed wiring that completes the final signal line connection under the direction of the global wiring, and detailed wiring. Therefore, designing a global wiring method for 2.5D Chiplet packages, and under the condition of meeting rule constraint, completing layer allocation and reducing wiring length becomes a problem to be solved in the current technical field. Disclosure of Invention The invention mainly aims to provide a Chiplet-oriented automatic wiring method for completing global wiring of 2.5D Chiplet packages. In order to solve the technical problems, the technical scheme adopted by the invention is as follows: In a first aspect, the present invention provides an automatic wiring method for Chiplet, the method comprising: step S1, preprocessing, namely acquiring Chiplet wiring data, splitting a multi-terminal wire network into two-terminal wire networks, carrying out via planning and end point distribution of an FA wire network, and constructing global wiring map resources by utilizing Voronoi grids; step S2, performing grouping, layer distribution, escape line sequence planning, escape point determination and perforation area and wiring area division on the Inter-Chip network, and selecting an optimal fan-out mode for each network to determine via holes; And step S3, 3D-A routing, wherein the routing is performed by using a 3D-A algorithm with cross perception based on global wiring map resources and planning results. By adopting the technical scheme, the via programming comprises: (1) Pre-processing via hole planning; For the PA wire mesh, a via hole is arranged at the position corresponding to the I/O pad and the bump pad in each redistribution layer; For the FA network, the bump pad positions of the FA network are optimized by using a simulated annealing algorithm SA to convert the FA network into the PA network, and through holes are arranged at positions corresponding to the I/O pads and the bump pads in each layer of redistribution layer, wherein the optimization targets of the simulated annealing algorithm SA comprise the crossing number of flying wires and the wire length of the flying wires; (2) Performing final treatment on the via hole planning; Equally dividing the wiring map into areas with the same size; Projecting the information of the I/O pads, the Bump pads and the through holes of the upper layer and the information of the C4 Bump layer to the current redistribution layer, and generating a new through hole in the center of the area if the number of the pads in the projected area is smaller than a preset number value; after the global routing is completed, unused vias are deleted. With the technical scheme, the initial solution of the SA is simulatedSelecting the latest b