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CN-121997882-A - Method, product, method and storage medium for removing pessimistic margin of public path

CN121997882ACN 121997882 ACN121997882 ACN 121997882ACN-121997882-A

Abstract

The invention relates to the technical field of pessimistic degree elimination algorithms, in particular to a method, a product, a method and a storage medium for removing pessimistic margin of a public path, which comprises the steps of providing a clock tree, traversing the clock tree, and generating an index table, a sequence table and a hierarchy table based on information obtained by traversing; generating a line segment tree based on the sequence table and the hierarchy table, inquiring the start point and the end point of any given time sequence path through the line segment tree to obtain the nearest public node, determining a subtree modified in the optimization process based on the nearest public node, correspondingly modifying the index table, the sequence table and/or the hierarchy table, and then carrying out the pessimistic margin removal analysis of the public path to remove the pessimistic margin. The method provided by the invention can solve the technical problem that the current method for removing the pessimistic margin of the public path consumes more time.

Inventors

  • HAN JUN

Assignees

  • 华芯巨数(杭州)微电子有限公司

Dates

Publication Date
20260508
Application Date
20241101

Claims (10)

  1. 1. A method for removing pessimistic margin of a common path for timing analysis on an integrated circuit, comprising: Providing a clock tree, traversing the clock tree, and generating an index table, a sequence table and a hierarchy table based on information obtained by traversing; generating a line segment tree based on the order table and the hierarchy table; for the starting point and the end point of any given time sequence path, obtaining the nearest public node through line segment tree inquiry; and based on the nearest public node, determining a subtree modified in the optimization process, correspondingly modifying an index table, a sequence table and/or a hierarchy table, and then carrying out the pessimistic margin removal analysis of the public path to remove the pessimistic margin.
  2. 2. The method of claim 1, wherein providing a clock tree, traversing the clock tree, and generating an index table, a sequence table, and a hierarchy table based on the information obtained by the traversing comprises: providing a clock tree, traversing the clock tree, and acquiring each device in the integrated circuit; corresponding indexes of all devices are recorded in an index table; Acquiring the access sequence of the device according to the index table, and recording the sequence in the sequence table; when encountering a device which is not recorded in the index table, adding the corresponding device name into the index table; the hierarchy of accessing devices on the clock tree is obtained, and the corresponding hierarchy of devices is recorded in a hierarchy table.
  3. 3. The method of claim 1, wherein generating the line segment tree based on the order table and the hierarchy table comprises: providing a starting point and an ending point of a time sequence path, and judging the sizes of the starting point and the ending point; If the starting point is greater than the ending point, dividing two subintervals in the current time sequence path interval, recording a maximum value and a minimum value in the current whole interval, and respectively recursively constructing a line segment tree in the two subintervals; If the starting point is equal to the end point, constructing leaf nodes of the line segment tree based on the current value; and if the starting point is greater than the end point, returning to provide the starting point and the end point of the time sequence path.
  4. 4. The method of claim 1, wherein for any given starting point and ending point of the timing path, obtaining the nearest common node by segment tree query comprises: for the start point and the end point of any given time sequence path, determining a device and an index thereof based on an index table; obtaining a minimum index through line segment tree query; And inquiring in the hierarchical table based on the minimum value index to obtain a corresponding device, wherein the corresponding device is the nearest public node.
  5. 5. A common path pessimistic margin removal method as recited in claim 1, wherein the optimization process includes an adjustment operation and an insertion operation.
  6. 6. The method of claim 5, wherein the adjusting operation comprises: The integrated circuit comprises a plurality of library modules, and when one library module in the integrated circuit is replaced, the index of the replaced library module is updated on the index table.
  7. 7. The method of common path pessimistic margin removal of claim 5, wherein the inserting operation comprises: Determining subintervals in which devices need to be inserted based on the nearest public node; The corresponding subtree level is incremented by 1, and the corresponding level table is modified based on the subtree.
  8. 8. A computer program product comprising a computer program which, when executed by a processor, implements the common path pessimistic margin removal method of any one of claims 1 to 7.
  9. 9. A computer device comprising a memory, a processor and a computer program stored on the memory, the processor executing the computer program to perform the steps of the common path pessimistic margin removal method of any one of claims 1 to 7.
  10. 10. A computer-readable storage medium, on which a computer program is stored, characterized in that the computer program, when executed by a processor, implements the steps of the common path pessimistic margin removal method of any one of claims 1 to 7.

Description

Method, product, method and storage medium for removing pessimistic margin of public path [ Field of technology ] The present invention relates to the technical field of pessimistic level elimination algorithms, and in particular, to a method, a product, a method, and a storage medium for removing pessimistic level of a common path. [ Background Art ] The computing process tends to be pessimistic in order to prevent the problem of non-convergence in the signoff (signature) stage in the timing analysis. Such as setup check analysis SIGNAL PATH, may analyze according to maximum delay, but excessive pessimistic may result in the direct discarding of many of the available resources at the time of layout design, thus requiring the removal of unreasonable pessimistic margins. CPPR (common clock PATH PESSIMISM remote) is one of the common methods for removing pessimistic margin, and is repeatedly used in timing analysis. A common overlapping path easily appears between a capture path and a launch path of TIMING PATH (timing path), and the launch path and the capture path are analyzed in accordance with constraints of min (minimum) and max (maximum), respectively, at the time of timing analysis, which is an unnecessary behavior on a common path, because the common path does not overlap with both the minimum and maximum constraints at a certain time, so that pessimistic margin introduced by the common path needs to be removed at the time of judging whether the timing path converges. The key step of the common path pessimistic margin removal analysis is to determine the longest common point (common node) from the clock, and after determining the nearest common point, only the difference between the arrival times of the transmit path and the capture path to this common point, the pessimistic margin, needs to be calculated. A currently more common method of finding a common point is forward trace back, looking forward after PATH START (timing path start) and path end (timing path end) are determined, until the longest common node is found. This mechanism, like the exhaustive method, tends to consume more time on complex layouts, and significant increases in time and memory consumption occur with increases in the number of TIMING PATH (timing paths). In addition to forward trace back, there are look-up methods similar to those that first build a discrete table. Firstly, performing one-pass exhaustive traversal on the netlist, recording the connection relation between devices, and then establishing a discrete table to record the minimum element in the interval corresponding to any two device traversal sequences. And when the pessimistic margin is calculated, searching in a discrete table according to the device corresponding index, wherein the minimum element in the given interval is the nearest public node. The time and space consuming of this approach is reduced relative to the previous forward trace, but the original look-up table is directly unavailable when the netlist is modified, requiring a first traverse of the clock tree and then creation of the hash table, which is time consuming. [ Invention ] In order to solve the technical problem that the current method for removing the pessimistic margin of the public path consumes more time, the invention provides the method, the product, the method and the storage medium for removing the pessimistic margin of the public path. The invention provides a method for removing pessimistic margins of a public path, which comprises the steps of providing a clock tree, traversing the clock tree, generating an index table, a sequence table and a level table based on information obtained by traversing, generating a line segment tree based on the sequence table and the level table, inquiring a start point and an end point of any given time sequence path through the line segment tree to obtain nearest public nodes, determining a subtree modified in an optimization process based on the nearest public nodes, correspondingly modifying the index table, the sequence table and/or the level table, and then carrying out public path pessimistic margin removal analysis to remove the pessimistic margins. Preferably, providing a clock tree, traversing the clock tree, and then generating an index table, a sequence table and a hierarchy table based on information obtained by traversing the clock tree, wherein the clock tree is provided, traversing the clock tree, obtaining each device in the integrated circuit, correspondingly indexing each device in the index table, recording the sequence in the sequence table according to the sequence of accessing the index table, adding the corresponding device name into the index table when the device which is not recorded in the index table is encountered, obtaining the hierarchy of accessing the device on the clock tree, and recording the corresponding hierarchy of the device in the hierarchy table. Preferably, generating the line segment tree based on the s