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CN-121997885-A - Motherboard assembly stress simulation modeling method, electronic device and program product

CN121997885ACN 121997885 ACN121997885 ACN 121997885ACN-121997885-A

Abstract

The application provides a main board assembly stress simulation modeling method, electronic equipment and a program product, which can be used in the technical field of simulation modeling. The method comprises the steps of responding to a component selection operation of a user, selecting target components of a main board three-dimensional model, wherein the target components comprise main boards, chips and bonding pad silk-screen wires, determining chip soldering tin based on the bonding pad silk-screen wires, conducting grid division on the chip soldering tin to obtain chip soldering tin grids, conducting grid division on the main boards to obtain main board grids, determining chip main bodies of chips based on soldering tin thicknesses of the chip soldering tin, conducting grid division on the chip main bodies to obtain chip grids, and establishing binding connection relations among grids of all target components based on constraint relations among all target components to obtain a stress simulation model. The method of the application remarkably improves the accuracy and modeling efficiency of the stress simulation modeling of the main board assembly.

Inventors

  • TIAN QI
  • FAN LIANGLIANG

Assignees

  • 东莞华贝电子科技有限公司

Dates

Publication Date
20260508
Application Date
20251222

Claims (10)

  1. 1. A motherboard assembly stress simulation modeling method, the method comprising: responding to the component selection operation of a user, and selecting a target component of the main board three-dimensional model, wherein the target component comprises a main board, a chip and a bonding pad silk-screen line; determining chip soldering tin based on the bonding pad silk-screen wire, and performing grid division on the chip soldering tin to obtain a chip soldering tin grid; Dividing grids of the main board to obtain main board grids; Determining a chip main body of the chip based on the soldering tin thickness of the chip soldering tin, and carrying out grid division on the chip main body to obtain a chip grid; And establishing binding connection relations among grids of all the target components based on constraint relations among all the target components to obtain a stress simulation model.
  2. 2. The method according to claim 1, wherein the method further comprises: extracting the middle surface of the main board; Based on the normal vector of the middle plane of the main board, establishing a local coordinate system taking the middle plane of the main board as a reference; Constructing a soldering tin geometric surface matched with the chip soldering tin based on the coordinate parameters of the chip soldering tin under the local coordinate system; And cutting the middle surface of the main board based on the soldering tin geometric surface, and determining the chip soldering tin area on the main board.
  3. 3. The method of claim 2, wherein the target component further comprises other components, the other components being resistive elements, capacitive elements, inductive elements, or connectors, the method further comprising, prior to establishing a binding connection between the respective grids of the target components based on the constraint relationship between the respective target components, obtaining a stress simulation model: Acquiring coordinate parameters of the other components under the local coordinate system; And carrying out grid division on the other parts based on the coordinate parameters to obtain grids of the other parts.
  4. 4. The method of claim 3, wherein the target component further comprises a shield, the method further comprising: Extracting the thickness of the shielding case; grid dividing the shielding case based on the thickness of the shielding case to obtain shielding case grids; Determining shielding cover soldering tin corresponding to the shielding cover based on the relative positions of the shielding cover and the main board; and carrying out grid division on the shielding cover soldering tin to obtain shielding cover soldering tin grids.
  5. 5. The method according to any one of claims 1-4, wherein meshing the motherboard to obtain a motherboard mesh comprises: extracting the thickness of the main board; And carrying out grid division on the main board based on the thickness of the main board to obtain the main board grid.
  6. 6. The method of any of claims 1-4, wherein determining a chip body of the chip based on a solder thickness of the chip solder comprises: and cutting the bottom of the chip based on the soldering tin thickness to determine the chip main body.
  7. 7. The method of any of claims 1-4, wherein meshing the chip body to obtain a chip mesh comprises: extracting the chip thickness of the chip main body; and dividing the grids of the chip main body based on the thickness of the chip to obtain the grids of the chip.
  8. 8. The method according to any one of claims 1-4, wherein the motherboard three-dimensional model is obtained based on the following method: obtaining a structural drawing of the main board assembly; and generating the mainboard three-dimensional model based on the geometric parameters in the structural drawing.
  9. 9. An electronic device comprising a processor, and a memory communicatively coupled to the processor; The memory stores computer-executable instructions; the processor executes computer-executable instructions stored in the memory to implement the method of any one of claims 1 to 8.
  10. 10. A computer program product comprising a computer program for implementing the method of any one of claims 1 to 7 when the computer program is executed.

Description

Motherboard assembly stress simulation modeling method, electronic device and program product Technical Field The present application relates to the field of simulation modeling technologies, and in particular, to a method for simulating stress of a motherboard assembly, an electronic device, and a program product. Background In the field of electronic equipment manufacturing, a chip is used as a core device of a main board assembly, and the reliability of welding between the chip and the main board directly determines the reliability of long-term operation of the electronic equipment. In order to avoid damage or crack of soldering tin caused by bearing multiple complex loads such as temperature circulation, mechanical vibration, thermal shock and the like between the chip and the main board, the chip is in desoldering failure, the chip desoldering risk is accurately judged, and the design and the process are optimized in advance, so that the chip and the main board become core requirements for guaranteeing the reliability of products in the field of electronic equipment manufacturing. In order to predict and avoid such risks, a stress simulation method is commonly adopted in the industry, and stress strain data of a chip soldering tin area is calculated by establishing a stress simulation model of a main board assembly, so that the chip solder-free risk is estimated and the structural optimization of the main board assembly is guided. The accurate simulation model of the main board assembly stress is a basis for ensuring accurate acquisition of the stress analysis result of the chip soldering tin area. However, the current main board assembly has the problems of complex operation and low accuracy in the stress simulation modeling process, so that accurate stress data of a chip soldering tin area on the main board cannot be accurately obtained, the accuracy of simulation data is insufficient, the correct optimization direction of the main board or the process is difficult to determine, and finally, the time cost and the labor cost of a project in the research and development process are obviously increased. Disclosure of Invention The application provides a main board assembly stress simulation modeling method, electronic equipment and a program product, which are used for solving the technical problems of complex operation and low accuracy of the existing main board assembly in the process of constructing a stress simulation model. According to a first aspect of the disclosure, the present application provides a method for modeling stress simulation of a motherboard assembly, the method comprising: responding to the component selection operation of a user, and selecting a target component of the main board three-dimensional model, wherein the target component comprises a main board, a chip and a bonding pad silk-screen line; determining chip soldering tin based on the bonding pad silk-screen wire, and performing grid division on the chip soldering tin to obtain a chip soldering tin grid; Dividing grids of the main board to obtain main board grids; Determining a chip main body of the chip based on the soldering tin thickness of the chip soldering tin, and carrying out grid division on the chip main body to obtain a chip grid; And establishing binding connection relations among grids of all the target components based on constraint relations among all the target components to obtain a stress simulation model. In a possible embodiment, the method further comprises: extracting the middle surface of the main board; Based on the normal vector of the middle plane of the main board, establishing a local coordinate system taking the middle plane of the main board as a reference; Constructing a soldering tin geometric surface matched with the chip soldering tin based on the coordinate parameters of the chip soldering tin under the local coordinate system; And cutting the middle surface of the main board based on the soldering tin geometric surface, and determining the chip soldering tin area on the main board. In a possible embodiment, the target component further includes other components, where the other components are resistive elements, capacitive elements, inductive elements, or connectors, and before establishing the binding connection between the grids of the target components based on the constraint relationship between the target components, the method further includes, before obtaining the stress simulation model: Acquiring coordinate parameters of the other components under the local coordinate system; And carrying out grid division on the other parts based on the coordinate parameters to obtain grids of the other parts. In a possible embodiment, the target component further comprises a shield, the method further comprising: Extracting the thickness of the shielding case; grid dividing the shielding case based on the thickness of the shielding case to obtain shielding case grids; Determining shielding cov