CN-121997982-A - Offset compensation method and device for defect position of epitaxial wafer and electronic equipment

Abstract

The application discloses an offset compensation method and device for defect positions of epitaxial wafers and electronic equipment, and belongs to the technical field of semiconductors. The method comprises the steps of obtaining prealignment parameters and first defect position information of a first epitaxial wafer, determining an offset compensation model based on an epitaxial wafer defect sample set, wherein the epitaxial wafer defect sample set comprises sample prealignment parameters, sample defect position information and defect position sample labels, and obtaining target defect position information of the first epitaxial wafer based on the prealignment parameters, the first defect position information and the offset compensation model. According to the method, the functional relation among the prealignment parameter, the original defect coordinate and the actual defect coordinate is accurately learned through the offset compensation model, so that the accurate compensation is carried out on the position offset of the epitaxial wafer defect, the reliable position mapping relation between the epitaxial wafer defect and devices such as chips is constructed, and the accuracy of subsequent yield analysis and the accuracy of process control are effectively improved.

Inventors

• QU DEQING

Assignees

• 安徽长飞先进半导体股份有限公司

Dates

Publication Date

20260508

Application Date

20251224

Claims (10)

1. 1. The method for compensating the offset of the defect position of the epitaxial wafer is characterized by comprising the following steps of: acquiring prealignment parameters and first defect position information of a first epitaxial wafer; Determining an offset compensation model based on an epitaxial wafer defect sample set, wherein the epitaxial wafer defect sample set comprises sample pre-alignment parameters, sample defect position information and defect position sample labels; And obtaining target defect position information of the first epitaxial wafer based on the pre-alignment parameters, the first defect position information and the offset compensation model.
2. 2. The method for compensating for the offset of the defect position of the epitaxial wafer according to claim 1, wherein the sample pre-alignment parameter and the sample defect position information are test data of a sample epitaxial wafer which is not subjected to zero layer lithography; and the defect position sample label is the test data of the sample epitaxial wafer subjected to zero-layer lithography.
3. 3. The method for offset compensation of epitaxial wafer defect locations of claim 1, wherein determining an offset compensation model based on the epitaxial wafer defect sample set comprises: Obtaining a sample prediction defect position based on the sample pre-alignment parameter, the sample defect position information and the offset compensation model to be trained; Determining a model loss function based on the sample predicted defect location and the defect location sample label; and updating model parameters of the offset compensation model based on the model loss function to obtain the trained offset compensation model.
4. 4. The method of claim 3, wherein updating model parameters of the offset compensation model based on the model loss function comprises: And based on the model loss function, adopting an adaptive moment estimation optimizer to iteratively update the model parameters.
5. 5. The method for offset compensation of epitaxial wafer defect locations of any one of claims 1-4, wherein the offset compensation model comprises an input layer, a residual network structure and an output layer connected in sequence, the residual network structure comprising a preset number of residual blocks connected in sequence.
6. 6. An offset compensation device for defect positions of epitaxial wafers is characterized by comprising: The acquisition module is used for acquiring prealignment parameters and first defect position information of the first epitaxial wafer; the first processing module is used for determining an offset compensation model based on an epitaxial wafer defect sample set, wherein the epitaxial wafer defect sample set comprises sample prealignment parameters, sample defect position information and defect position sample labels; And the second processing module is used for obtaining the target defect position information of the first epitaxial wafer based on the pre-alignment parameter, the first defect position information and the offset compensation model.
7. 7. The apparatus according to claim 6, wherein the sample pre-alignment parameter and the sample defect position information are test data of a sample epitaxial wafer for which zero layer lithography is not performed; and the defect position sample label is the test data of the sample epitaxial wafer subjected to zero-layer lithography.
8. 8. An electronic device comprising a memory, a processor and a computer program stored on the memory and executable on the processor, wherein the processor implements the method of offset compensation of epitaxial wafer defect locations according to any one of claims 1-5 when executing the program.
9. 9. A non-transitory computer readable storage medium having stored thereon a computer program, which when executed by a processor implements the offset compensation method of epitaxial wafer defect locations according to any one of claims 1-5.
10. 10. A computer program product comprising a computer program which, when executed by a processor, implements a method of offset compensation of epitaxial wafer defect locations according to any of claims 1-5.

Description

Offset compensation method and device for defect position of epitaxial wafer and electronic equipment Technical Field The application belongs to the technical field of semiconductors, and particularly relates to an offset compensation method and device for defect positions of epitaxial wafers and electronic equipment. Background In the epitaxial wafer growth process, defects are inevitably generated due to the influence of various factors such as growth conditions, material characteristics, process parameters and the like. After the epitaxial process, the quality of the epitaxial wafer can be detected by an epitaxial measuring machine, defects on the epitaxial wafer are identified, and the coordinate positions and the size information of the defects are recorded for subsequent yield analysis and process control. At present, when an epitaxial measurement machine detects the defects of the epitaxial wafer, the coordinate alignment is carried out only by a mechanical alignment device, so that larger deviation exists between the detected defect position and the actual physical position of the defects, and the subsequent yield analysis and process control are affected. Disclosure of Invention The present invention aims to solve at least one of the technical problems existing in the prior art. Therefore, the invention provides a deviation compensation method and device for the defect position of an epitaxial wafer and electronic equipment, which can accurately compensate the deviation of the defect position of the epitaxial wafer. In a first aspect, the present application provides a method for compensating for offset of a defect position of an epitaxial wafer, the method comprising: acquiring prealignment parameters and first defect position information of a first epitaxial wafer; Determining an offset compensation model based on an epitaxial wafer defect sample set, wherein the epitaxial wafer defect sample set comprises sample pre-alignment parameters, sample defect position information and defect position sample labels; And obtaining target defect position information of the first epitaxial wafer based on the pre-alignment parameters, the first defect position information and the offset compensation model. According to the offset compensation method for the defect position of the epitaxial wafer, disclosed by the application, the prealignment parameters and the first defect position information of the first epitaxial wafer are input into the offset compensation model, the offset compensation model is used for carrying out offset compensation on the defect coordinates to obtain the target defect position information output by the offset compensation model, the offset compensation model is used for accurately learning the functional relation among the prealignment parameters, the original defect coordinates and the actual defect coordinates to accurately compensate the defect position offset of the epitaxial wafer, so that the construction of a reliable position mapping relation between the epitaxial wafer defects and devices such as chips is facilitated, and the accuracy of subsequent yield analysis and the accuracy of process control are effectively improved. According to one embodiment of the present application, the sample pre-alignment parameter and the sample defect position information are test data of a sample epitaxial wafer without zero layer lithography; and the defect position sample label is the test data of the sample epitaxial wafer subjected to zero-layer lithography. According to one embodiment of the present application, the determining an offset compensation model based on the epitaxial wafer defect sample set includes: Obtaining a sample prediction defect position based on the sample pre-alignment parameter, the sample defect position information and the offset compensation model to be trained; Determining a model loss function based on the sample predicted defect location and the defect location sample label; and updating model parameters of the offset compensation model based on the model loss function to obtain the trained offset compensation model. According to one embodiment of the present application, the updating the model parameters of the offset compensation model based on the model loss function includes: And based on the model loss function, adopting an adaptive moment estimation optimizer to iteratively update the model parameters. According to one embodiment of the application, the offset compensation model comprises an input layer, a residual network structure and an output layer which are connected in sequence, wherein the residual network structure comprises a preset number of residual blocks connected in sequence. In a second aspect, the present application provides an offset compensation apparatus for defect positions of epitaxial wafers, the apparatus comprising: The acquisition module is used for acquiring prealignment parameters and first defect position information of t