CN-121997995-A - Neural network acceleration core capable of reducing single pixel errors and intelligent driving chip

CN121997995ACN 121997995 ACN121997995 ACN 121997995ACN-121997995-A

Abstract

The invention relates to a neural network acceleration core for reducing single pixel errors and an intelligent driving chip, wherein the acceleration core comprises a plurality of quick calculation modules Cal for realizing multiplication-before-addition convolution, the quick calculation modules Cal are divided into m groups of calculation cores, each group of calculation cores comprises n quick calculation modules Cal and a polling check calculation module Cal pair, the polling check calculation module Cal pair is used for inputting the same value with the same group of n quick calculation modules Cal in turn, and comparing whether calculation results are consistent or not so as to ensure that the quick calculation modules Cal have no errors and avoid permanent failure of the quick calculation modules Cal. The method has the beneficial effects of coping with traffic accidents caused by logic errors of adders and multipliers due to random hardware failure and further generating single pixel errors, and providing a high-efficiency and high-safety solution.

Inventors

HANG ZHANGJUN
WANG LEI
CHEN GUO
PENG XIAOFENG

Assignees

北京辉羲智能科技有限公司

Dates

Publication Date: 20260508
Application Date: 20241104

Claims (9)

1. The neural network acceleration core for reducing single pixel errors comprises a plurality of quick calculation modules Cal for realizing multiplication-before-addition convolution, and is characterized in that the quick calculation modules Cal are divided into m groups of calculation cores, each group of calculation cores comprises n quick calculation modules Cal and a polling check calculation module Cal pair, the polling check calculation modules Cal pair are used for inputting the same value with the same group of n quick calculation modules Cal in turn and comparing whether calculation results are consistent or not so as to ensure that the quick calculation modules Cal have no errors and avoid permanent failure of the quick calculation modules Cal.
2. A neural network acceleration core for reducing single pixel errors of claim 1, further comprising a first switch for alternately switching the same set of fast computation module Cal inputs to the poll-check computation module Calpair inputs per clock cycle, and a second switch for alternately switching the same set of fast computation module Cal outputs and the poll-check computation module Cal pair outputs for each clock cycle.
3. The neural network acceleration core for reducing single pixel errors of claim 2, wherein the configuration ratio of the fast calculation module Cal and the poll check calculation module Cal pair of each group of calculation cores is n:1, N < = FDTI/F, FDTI is a fault detection interval meeting road vehicle function safety standard ISO26262, and F is an image acquisition time of each frame of an image processed by the neural network acceleration core.
4. A neural network acceleration core that reduces single pixel errors, as set forth in claim 2, wherein the poll-check computation module Cal pair does not compare-check the fast computation module Cal set to be security-independent.
5. The neural network acceleration core of claim 2, further comprising a separate check computation module for inputting the same value to the fast computation module Cal that needs to identify temporary failures for each clock cycle, and comparing whether the computation results are consistent, so as to ensure that the fast computation module Cal has no errors and avoid permanent failures of the fast computation module Cal.
6. An intelligent driving chip for reducing single pixel errors, which is characterized by comprising the neural network acceleration core for reducing single pixel errors according to any one of claims 1 to 5.
7. The intelligent driving chip for reducing single pixel errors according to claim 6, comprising a processor, wherein the processor executing the intelligent driving program to cope with a failure of a convolution layer caused by the single pixel errors in intelligent driving comprises the steps of: S1, extracting a characteristic value by convolution to be used for identification, and not considering that the same error occurs twice; s2, identifying A; s3, identifying B; s4, selecting A or B with low safety hazard identified.
8. The intelligent driving chip for reducing single pixel errors according to claim 7, wherein the processor executing the intelligent driving program when the object recognition scene is to cope with a failure of a convolution layer caused by the single pixel errors in intelligent driving comprises the steps of: s1, extracting a characteristic value by convolution to be used for identifying a target object, and not considering that the same error occurs twice; s2, identifying unexpected targets; S3, not identifying the target object; s4, selecting and identifying unexpected targets.
9. The intelligent driving chip for reducing single pixel errors according to claim 7, wherein the processor executing the intelligent driving program when the traffic light scene is corresponding to the failure of the convolution layer caused by the single pixel errors during intelligent driving comprises the following steps: s1, extracting a characteristic value by convolution to be used for traffic light identification, and not considering that the same error occurs twice; S2, identifying a red light; s3, identifying green light; s4, selecting and identifying the red light.

Description

Neural network acceleration core capable of reducing single pixel errors and intelligent driving chip [ Field of technology ] The invention relates to the technical field of automobile electronics, in particular to a neural network acceleration core and an intelligent driving chip for reducing single pixel errors. [ Background Art ] The automobile electronic chip realizes the design which is highly reliable and meets the requirements of the functional safety ISO26262 standard. ISO26262 is an international functional safety standard, specifically for electrical and/or electronic systems in road vehicles, including those involving safety-related functions. The chip is inevitably subject to random hardware failure due to environmental and aging factors. Random hardware failure can generate single pixel errors, such as certain adder, multiplier logic errors. The change of a single pixel can have a significant impact on the image recognition and processing system and may even cause the system to erroneously recognize or process an image. For intelligent driving, some fault injection experiments are performed in the industry. Single pixel errors are injected into different layers of the neural network, and after the errors are injected, the number, the position or the size of the target possibly change, so that the target detection and the distance judgment are influenced. In a high-level automatic driving system, an error caused by a single pixel may cause traffic accidents to occur. There are 2 existing classical neural network accelerator security designs. One is realized by a logic part DCLS (dual core lockstep architecture), and the realization mode of the DCLS has too great loss of power consumption, chip area and the like because the neural network calculation needs a large amount of calculation force. The second is that the permanent failure can only be identified by the online BIST, the temporary failure can not be identified, and the online BIST has higher requirements on software scheduling and chip design. BIST is a technique for providing a self-test function by embedding relevant functional circuits in a circuit at design time, thereby reducing the dependency of device testing on Automatic Test Equipment (ATE). For a temporary failure of a high-level autopilot system, errors caused by a single pixel may lead to the occurrence of traffic accidents. In a Uber accident, NTSB issues a survey report detailing the pre-crash timeline, such as the system's recognition of the pedestrian swaying between "vehicle" and "others" 2.7 to 3.8 seconds before the crash, the system recognizes the pedestrian and her bicycle as "bicycle" 2.6 seconds from the crash, then the pedestrian is recognized as "unknown" by the system 1.5 seconds from the crash, and the 1.2 second recognition before the crash becomes bicycle. The result is to turn around and switch continuously, finally resulting in the occurrence of the accident. Aiming at the technical problems that logic errors of adders and multipliers are caused by random hardware failure in a high-level automatic driving chip, and traffic accidents are caused by single pixel errors, the invention carries out technical improvement on a neural network acceleration core and an intelligent driving chip. [ Invention ] The invention aims to provide an intelligent driving main control chip internal neural network acceleration core which is high in efficiency and high in safety and can deal with traffic accidents caused by logic errors of adders and multipliers and single pixel errors generated by random hardware failure. In order to achieve the above purpose, the technical scheme adopted by the invention is that the neural network acceleration core for reducing single pixel errors comprises a plurality of fast calculation modules Cal for realizing multiplication-before-addition convolution, wherein the fast calculation modules Cal are divided into m groups of calculation cores, each group of calculation cores comprises n fast calculation modules Cal and a polling check calculation module Cal pair, and the polling check calculation module Cal pair is used for inputting the same value with the same group of n fast calculation modules Cal in turn and comparing whether calculation results are consistent or not so as to ensure that the fast calculation modules Cal have no errors and avoid permanent failure of the fast calculation modules Cal. Preferably, each group of computing cores further comprises a first switcher for alternately switching the same group of fast computing modules Cal input to the poll-check computing module Cal pair input every clock period, and a second switcher for alternately switching the same group of fast computing modules Cal output and the poll-check computing module Cal pair output comparison every clock period. Preferably, the configuration ratio of the fast calculation module Cal and the polling check calculation module Cal pair of each group of calculat