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CN-121998003-A - Neuron circuit, activation and preparation method, neural network and signal processing system

CN121998003ACN 121998003 ACN121998003 ACN 121998003ACN-121998003-A

Abstract

The invention provides a neuron circuit which comprises n input tubes, an integral capacitor, an inversion output unit and a reset unit, wherein the input tubes select one gate based on input voltage and control voltage, the integral capacitor is released after accumulating charges, the inversion output unit generates output voltage, and the reset unit resets the potential of the integral capacitor. The invention also provides an activation method of the neuron circuit, which activates the neuron circuit by controlling the discharge after the integration capacitor accumulates charges. The invention also provides a preparation method of the field effect transistor, and a source electrode structure, a drain electrode structure and a grid electrode structure are formed on the provided substrate. The invention also provides a neural network comprising an input layer and an output layer, wherein the output end of a single neuron circuit of the input layer is connected with the input ends of all or part of neuron circuits of the output layer. The signal processing system comprises an electric signal input device, a reading device and a neural network, wherein the electric signal input device provides input data, and the reading device reads output data.

Inventors

  • BAO WENZHONG

Assignees

  • 原集微(上海)电子有限公司

Dates

Publication Date
20260508
Application Date
20260403

Claims (15)

  1. 1. The neuron circuit is characterized by at least comprising n input tubes, an integrating capacitor, an inverting output unit and a reset unit, wherein n is a natural number greater than or equal to 1; The input ends of the n input tubes are correspondingly connected with n input voltages one by one, the control ends are correspondingly connected with n control voltages one by one, and the output ends are respectively connected with the first polar plates of the integrating capacitors; the second polar plate of the integrating capacitor is grounded; the input end of the inverting output unit is connected with the first polar plate of the integrating capacitor, and the power supply end is connected with external voltage; The control end of the reset unit is controlled by the output end of the inverting output unit, the input end of the reset unit is connected with reset voltage, and the output end of the reset unit is connected with the first polar plate of the integrating capacitor.
  2. 2. The neuron circuit according to claim 1, wherein the inverting output unit comprises a first transistor and a second transistor; The input end of the second transistor is used as the output end of the inverting output unit, and the output end of the second transistor is grounded; The control end of the first transistor is connected with the external voltage, and the control end of the second transistor is connected with the first polar plate of the integrating capacitor; or the control end of the first transistor is connected with the first polar plate of the integrating capacitor, and the control end of the second transistor is grounded.
  3. 3. The neuron circuit according to claim 1, wherein the reset unit comprises a trigger and a reset control tube; the control end of the trigger is controlled by the output end of the reversed phase output unit, and the output end is connected with the control end of the reset control tube; The input end of the reset control tube is connected with the reset voltage, and the output end of the reset control tube is connected with the first polar plate of the integrating capacitor.
  4. 4. The neuron circuit according to any one of claims 1 to 3, further comprising m shaping elements, m being a natural number equal to or greater than 1, the m shaping elements being serially connected in sequence after the output of the inverting output unit.
  5. 5. The neuron circuit according to claim 4, wherein the control terminal of the reset unit is connected to the output terminal of any one of the shaping elements.
  6. 6. A method of activating a neuronal circuit based on the neuronal circuit implementation of any of claims 1-5, characterized in that the method of activating a neuronal circuit comprises at least the steps of: s1, selecting a gating input tube based on input voltage and control voltage, and accumulating charges by an integrating capacitor; And S2, controlling the control voltage to disconnect the input tube, discharging the integration capacitor, and activating the neuron circuit when the integration capacitor is discharged and the output voltage of the output end of the inverting output unit is turned to be high.
  7. 7. A method of activating a neuronal circuit based on the neuronal circuit implementation of any of claims 1-5, characterized in that the method of activating a neuronal circuit comprises at least the steps of: s1, providing a light source, wherein the light source irradiates an input tube alternatively, the input tube is conducted based on input voltage and control voltage, and an integrating capacitor accumulates charges; And S2, controlling the control voltage to disconnect the input tube, discharging the integration capacitor, and activating the neuron circuit when the integration capacitor is discharged and the output voltage of the output end of the inverting output unit is turned to be high.
  8. 8. The method for activating a neuron circuit according to claim 6 or 7, wherein in step S1, the control voltage or the input voltage is adjusted based on a luminance value of stray ambient light when the neuron circuit is used for image processing.
  9. 9. A method for manufacturing a field effect transistor, at least for manufacturing an input tube in a neuron circuit according to any one of claims 1 to 5, characterized in that the method for manufacturing a field effect transistor comprises at least the steps of: S1, providing a substrate, and forming a two-dimensional semiconductor material layer on the substrate; and S2, carrying out graphical processing on the two-dimensional semiconductor material layer, and forming a source electrode structure, a drain electrode structure and a grid electrode structure on the two-dimensional semiconductor material layer to form the field effect transistor.
  10. 10. The method of manufacturing a field effect transistor according to claim 9, wherein in step S1, the two-dimensional semiconductor material layer is made of a transition metal chalcogenide.
  11. 11. The neural network is characterized by at least comprising an input layer and an output layer; the input layer comprises u neuron circuits according to any one of claims 1 to 5, u being a natural number of 1 or more; the output end of the single neuron circuit of the input layer is connected with the input ends of all the neuron circuits of the output layer or the input ends of partial neuron circuits connected with the output layer; The input end of the neuron circuit is uniformly set as the input end of the input tube, the weight end of the neuron circuit is uniformly set as the control end of the input tube, or the input end of the neuron circuit is uniformly set as the control end of the input tube, the weight end of the neuron circuit is uniformly set as the input end of the input tube, and the output end of the neuron circuit is uniformly set as the output end of the inverting output unit.
  12. 12. The neural network of claim 11, wherein when the neuron circuit further comprises one or more shaping elements, the outputs of the neuron circuit are uniformly arranged as the outputs of the shaping elements.
  13. 13. The neural network of claim 11 or 12, further comprising one or more intermediate layers, said intermediate layers comprising one or more of said neuron circuits; The middle layer is sequentially arranged between the input layer and the output layer, and the output end of a single neuron circuit of any adjacent layer is connected with the input ends of all neuron circuits of the next layer or the input ends of partial neuron circuits of the next layer.
  14. 14. A signal processing system, characterized in that the signal processing system at least comprises an electrical signal input device, a readout device and the neural network according to any one of claims 11-13; The reading device is connected with the output end of each neuron circuit of the output layer.
  15. 15. The signal processing system of claim 14, further comprising a light source that illuminates an input tube to be gated of each neuron circuit of the input layer.

Description

Neuron circuit, activation and preparation method, neural network and signal processing system Technical Field The present invention relates to the field of semiconductor devices, integrated circuits, and neuromorphic computation, and more particularly, to a neuronal circuit, activation and fabrication methods, a neural network, and a signal processing system. Background Along with the rapid development of the edge computing scenes such as the internet of things, automatic driving, mobile robots and the like, the demand for localized intelligent hardware capable of carrying out real-time and efficient information processing is urgent. Conventional von neumann computing architectures often face memory wall bottlenecks and high power challenges when dealing with such tasks. In contrast, neuromorphic calculations inspired by the human brain, through pulse information processing mechanisms that mimic biological neurons and synapses, exhibit extremely high energy efficiency ratios and parallel processing potential. The core of the construction of neuromorphic hardware is to implement artificial neurons and synapses that function similar to biological neurons. Current research focuses mostly on device implementations of synaptic plasticity (e.g., long-term enhancement, pulse time dependent plasticity). However, there is a disadvantage in that the neuron modulation parameters are limited by adjusting the neuron circuit only by one adjustment mechanism. On the other hand, in the processing of computer vision, the existing neural network needs to perform conversion between optical and electrical signals, and then process the electrical signals based on the neural network, which also has a certain room for improvement. Therefore, how to provide a neuron circuit, an activation and preparation method, a neural network and a signal processing system capable of simultaneously realizing intrinsic plasticity modulation, light sensing calculation integration and pulse integration and release has become one of the technical problems to be solved by those skilled in the art. It should be noted that the foregoing description of the background art is only for the purpose of providing a clear and complete description of the technical solution of the present invention and is presented for the convenience of understanding by those skilled in the art. The above-described solutions are not considered to be known to the person skilled in the art simply because they are set forth in the background of the invention section. Disclosure of Invention In view of the above-mentioned drawbacks of the prior art, an object of the present invention is to provide a neuron circuit, an activation and preparation method, a neural network and a signal processing system, which are used for solving the problems of limited neuron modulation parameters, large calculation amount of visual processing and high power consumption of signal issuing in the prior art. In order to achieve the above object and other related objects, the invention provides a neuron circuit, which at least comprises n input tubes, an integral capacitor, an inverting output unit and a reset unit, wherein n is a natural number greater than or equal to 1, the input ends of the n input tubes are connected with n input voltages in a one-to-one correspondence manner, the control ends are connected with n control voltages in a one-to-one correspondence manner, the output ends are all connected with a first polar plate of the integral capacitor, a second polar plate of the integral capacitor is grounded, the input end of the inverting output unit is connected with the first polar plate of the integral capacitor, the power end is connected with an external voltage, the control end of the reset unit is controlled by the output end of the inverting output unit, the input end of the reset unit is connected with a reset voltage, and the output end of the reset unit is connected with the first polar plate of the integral capacitor. The inverting output unit comprises a first transistor and a second transistor, wherein the input end of the first transistor is connected with external voltage, the output end of the first transistor is connected with the input end of the second transistor, the input end of the second transistor is used as the output end of the inverting output unit, the output end of the second transistor is grounded, the control end of the first transistor is connected with the external voltage, the control end of the second transistor is connected with the first polar plate of the integrating capacitor, or the control end of the first transistor is connected with the first polar plate of the integrating capacitor, and the control end of the second transistor is grounded. Optionally, the reset unit comprises a trigger and a reset control tube, wherein the control end of the trigger is controlled by the output end of the inverting output unit, the output end of the trigger is connec