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CN-121998009-A - Method for on-line training and reasoning of neural network by using hybrid memory circuit based on CMOS transistor

CN121998009ACN 121998009 ACN121998009 ACN 121998009ACN-121998009-A

Abstract

The invention discloses a method for on-line training and reasoning of a neural network by a hybrid memory circuit based on a CMOS transistor, which adopts a CMOS transistor synaptic device and a CMOS capacitor to form a synaptic unit to replace a traditional memristor and a ferroelectric capacitor, the writing durability of the CMOS transistor synaptic device is far superior to that of the traditional memristor, the CMOS capacitor reading operation is nondestructive, the service life loss caused by data rewriting is avoided, meanwhile, the whole process is realized based on a standard CMOS process, the whole process is completely compatible with the existing integrated circuit manufacturing process, the hardware volume production cost is reduced, only analog weight is called for operation in the reasoning stage, no additional data transmission is needed, the weight transmission stage does not need an external DAC, the digital-analog conversion is realized by utilizing circuit parasitic parameters, and the energy expenditure of edge equipment is greatly reduced.

Inventors

  • ZHAO CHUN
  • WU RUI

Assignees

  • 深圳市华芯邦科技有限公司

Dates

Publication Date
20260508
Application Date
20260410

Claims (10)

  1. 1. The method for on-line training and reasoning of the neural network by using the hybrid memory circuit based on the CMOS transistor is characterized by comprising the following steps of: The method comprises the steps of S1, deploying a CMOS hybrid memory circuit, forming a synaptic unit by adopting a group of CMOS transistor synaptic devices and a group of CMOS capacitors, forming a hybrid memory array by a plurality of synaptic units, and providing a core weight storage and multiply-accumulate operation carrier for on-line training and reasoning of a neural network; S2, training on line based on a hybrid memory neural network, wherein the training comprises the following steps of; s21, performing forward propagation on each input sample by using the simulation weight of the synaptic device; S22, error back propagation and gradient calculation; S23, carrying out iterative updating on the digital hidden weights, carrying out digital updating on the hidden weights stored in the CMOS capacitor according to a gradient updating rule, wherein the updating probability is controlled by a binary mask; S24, weight timing transmission and analog weight programming, setting a sample updating threshold k, and triggering a weight transmission mechanism by a training control circuit after finishing S21-S23 operations of k training samples, so as to realize synchronous updating from digital hidden weights to analog weights; s3, based on-line reasoning of the training result of the neural network, a reasoning sample is input, and multiply-accumulate operation is carried out by using only the simulation weights stored in the CMOS transistor synapse device, so that low-power consumption reasoning is realized.
  2. 2. The method for on-line training and reasoning of neural network based on CMOS transistor as claimed in claim 1, wherein said CMOS transistor synapse devices are n-type MOSFETs and are connected in differential pair form to store positive and negative weights respectively, said CMOS capacitor array is composed of minimum size capacitors Cn to store 10 bit signed integer digital hidden weights in binary form And the most significant bit adopts 4x, 2x and 1x differential capacitance, a transmission line is connected between the grid electrode of the CMOS transistor synaptic device and the CMOS capacitance array, and the programming current of the synaptic device is directly controlled by loading voltage through parasitic capacitance.
  3. 3. The method for neural network on-line training and reasoning of the CMOS transistor-based hybrid memory circuit of claim 2, wherein the CMOS hybrid memory circuit deployment further comprises; The training control circuit is in control connection with the synapse unit through an integrated address decoder, a driving circuit, a sense amplifier and a time sequence control module, and is responsible for realizing accurate addressing of weight addresses, driving of weight updating, sense amplification of weight signals, time sequence coordination and logic control of each stage of training, reasoning and weight transmission in the neural network training process; Device pre-configuration by adjusting the body bias voltage of a CMOS transistor synaptic device via an additional MOSFET, configuring it to a synaptic mode, operating in the breakdown region and exhibiting a controlled resistance switching behavior, thereby simulating the long-term or short-term plasticity of the synapse.
  4. 4. The method for online training and reasoning of neural network based on the CMOS transistor hybrid memory circuit according to claim 3, wherein in the step S21, the training control circuit addresses the corresponding synapse cell through the address decoder by inputting the neural network training sample collected by the edge device into the hybrid memory array, and performs the inter-layer multiply-accumulate operation of the neural network by using the analog weight stored in the CMOS transistor synapse device, thereby realizing forward propagation and obtaining the predicted output result.
  5. 5. The method for on-line training and reasoning of the neural network according to claim 4, wherein the step S22 calculates the loss value by comparing the predicted output of the forward propagation with the real label of the sample, and based on a random gradient descent gradient update rule, the backward propagation of the loss value is completed by the training control circuit, calculates the update gradient of the analog weight of each synapse cell layer by layer, and transmits the gradient signal to the control terminal of the corresponding CMOS capacitor array.
  6. 6. The method for online training and reasoning of the neural network according to claim 5, wherein in step S23, the training control circuit performs binary digital iterative update on the digital hidden weights stored in the CMOS capacitor array according to the gradient signal, and the update probability is controlled by a binary mask.
  7. 7. The method for on-line training and reasoning of neural network based on CMOS transistor as claimed in claim 6, wherein the most significant bit and sign bit of digital hidden weight in the CMOS capacitor array are read in parallel by the sense amplifier in step S24, and the analog voltage proportional to the digital weight storage value is generated on the transmission line by utilizing the voltage gradient characteristic of the differential area capacitor The transmission line applies voltage through parasitic capacitance And loading the current to the grid electrode of the CMOS transistor synaptic device, directly controlling the programming current of the CMOS transistor synaptic device, and further programming the conductance value of the CMOS transistor synaptic device to finish synchronous updating from digital hidden weight to analog weight.
  8. 8. The method for online training and reasoning of the neural network based on the CMOS transistor according to claim 7, wherein the neural network performs training convergence judgment in the later stage of online training, steps S21 to S24 are repeated, the training sample is continuously input and the weight updating and synchronization are completed until the loss function value of the neural network is reduced to a preset threshold value or reaches the maximum training iteration number, the online training is stopped, and the simulation weight stored in the synaptic device of the CMOS transistor is the optimal weight after the training is completed.
  9. 9. The method for on-line training and reasoning of the neural network based on the CMOS transistor hybrid memory circuit of claim 8, wherein the step S3 comprises; S31, inputting an inference sample, namely taking inference data acquired by the edge equipment in real time as a neural network input sample, and transmitting the neural network input sample to the hybrid memory array; s32, performing multiply-accumulate operation with low power consumption, wherein the training control circuit addresses the corresponding synaptic unit according to the neural network architecture of the reasoning task, only invokes the programmed optimal simulation weight in the CMOS transistor synaptic device, and completes the multiply-accumulate operation of each layer of the neural network.
  10. 10. The method for online training and reasoning of the neural network based on the CMOS transistor as claimed in claim 6, wherein the step S3 further comprises the steps of outputting and feeding back a reasoning result, amplifying an operation signal through a sense amplifier of the training control circuit to obtain a final reasoning output result of the neural network, transmitting the result to a display or execution module of the edge equipment to realize real-time output of the reasoning result, taking a reasoning error as a new gradient trigger signal if the edge equipment needs to perform incremental online training, and automatically triggering the online training process of the step S2 to realize iterative optimization of weights when the threshold is reached through a preset error threshold.

Description

Method for on-line training and reasoning of neural network by using hybrid memory circuit based on CMOS transistor Technical Field The invention relates to the technical fields of nerve morphology calculation, artificial intelligence hardware and integrated circuits, in particular to a method for on-line training and reasoning of a neural network by a hybrid memory circuit based on CMOS transistors. Background Along with the increase of application demands of artificial intelligence on edge devices, how to realize efficient online training and reasoning in a resource-limited environment becomes a key challenge, and in the prior art, a memristor and a ferroelectric capacitor are often adopted to construct a hybrid memory architecture so as to optimize the reasoning and training processes respectively. However, the scheme adopts the memristor array to store analog weights for reasoning, the ferroelectric capacitor array stores high-precision digital hiding weights for training, the weights are frequently updated in the ferroelectric capacitors in the training process, and the most significant bits of the weights are periodically transmitted to the memristors through a digital-analog conversion circuit to realize weight synchronization, the circuit has good energy efficiency and precision, but relies on non-standard CMOS materials, the process is complex, meanwhile, the memristors have the problems of low writing durability and high programming energy, and special materials such as doping are needed for the ferroelectric capacitorsThe compatibility with standard CMOS process is poor, the integration complexity is high, and the cost is high, so a solution based on the standard CMOS process is urgently needed to improve the reliability, reduce the cost and simplify the manufacturing flow. Disclosure of Invention The invention aims to provide a method for on-line training and reasoning of a neural network by using a hybrid memory circuit based on CMOS transistors, so as to solve the problems in the background art. In order to achieve the above purpose, the invention provides the following technical scheme that the method for on-line training and reasoning of the neural network by using the hybrid memory circuit based on the CMOS transistor comprises the following steps: The method comprises the steps of S1, deploying a CMOS hybrid memory circuit, forming a synaptic unit by adopting a group of CMOS transistor synaptic devices and a group of CMOS capacitors, forming a hybrid memory array by a plurality of synaptic units, and providing a core weight storage and multiply-accumulate operation carrier for on-line training and reasoning of a neural network; S2, training on line based on a hybrid memory neural network, wherein the training comprises the following steps of; s21, performing forward propagation on each input sample by using the simulation weight of the synaptic device; S22, error back propagation and gradient calculation; S23, carrying out iterative updating on the digital hidden weights, carrying out digital updating on the hidden weights stored in the CMOS capacitor according to a gradient updating rule, wherein the updating probability is controlled by a binary mask; S24, weight timing transmission and analog weight programming, setting a sample updating threshold k, and triggering a weight transmission mechanism by a training control circuit after finishing S21-S23 operations of k training samples, so as to realize synchronous updating from digital hidden weights to analog weights; s3, based on-line reasoning of the training result of the neural network, a reasoning sample is input, and multiply-accumulate operation is carried out by using only the simulation weights stored in the CMOS transistor synapse device, so that low-power consumption reasoning is realized. Preferably, the CMOS transistor synaptic devices adopt n-type MOSFETs and are connected in a differential pair mode, and positive and negative weights W+ and W-; the CMOS capacitor array is composed of minimum size capacitors Cn, and stores digital hidden weights of 10-bit signed integers in binary form And the most significant bit adopts 4x、2x1XIs a differential capacitance of (2); A transmission line is connected between the grid electrode of the CMOS transistor synaptic device and the CMOS capacitor array, and parasitic capacitance is used for connecting the transmission line and the CMOS capacitor array Direct control of synaptic device programming current by applied voltage。 Preferably, the CMOS hybrid memory circuit arrangement further comprises; The training control circuit is used for realizing accurate addressing of weight addresses, driving of weight updating, sensing amplification of weight signals, time sequence coordination and logic control of each stage of training, reasoning and weight transmission in the neural network training process and ensuring the cooperative work of each hardware module through integrating an address de