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CN-121998948-A - Front and back chip graph data comparison method based on feature matching technology

CN121998948ACN 121998948 ACN121998948 ACN 121998948ACN-121998948-A

Abstract

The invention discloses a front and back chip graph data comparison method based on a feature matching technology, which relates to the technical field of semiconductor chip manufacturing and comprises the specific steps of data acquisition, model construction, feature matching, detection execution and result output; the method comprises the steps of constructing an improved SuperPoint model, introducing feature descriptor normalization processing, screening effective key point pairs by combining a joint matching model, establishing a projection transformation relation between a source image and a target image by utilizing a homography matrix, and realizing full-area uniform sampling and feature comparison by gridding difference detection.

Inventors

  • Men Kerun
  • HE ZHIGANG
  • JI HANG

Assignees

  • 中国工程物理研究院计量测试中心

Dates

Publication Date
20260508
Application Date
20260127

Claims (10)

  1. 1. A method for comparing front and back chip graphic data based on a feature matching technology is characterized by comprising the following specific steps: Collecting opening detection images of different batches of chips of the same model, covering chip layout images and bonding area images, collecting bonding solder ball images and ball key, wedge key and crescent key type images, marking a bonding pad, a solder ball area and bonding types, and dividing a training set and a testing set; Constructing a model, namely constructing an improved SuperPoint model based on the acquired annotation image and the divided training set and test set, constructing a joint matching model by integrating the improved SuperPoint model and the SuperGlue module, embedding BoTNet modules in a YOLOv-seg example segmentation model to complete optimization, constructing a bonding type recognition model based on a YOLOv8 framework, and inputting the training set to complete parameter iterative optimization of each model; Feature matching, namely converting an acquired chip layout image into a specified dimension tensor, inputting a trained improved SuperPoint model to extract a feature subset, inputting the feature subset into a joint matching model to output key point pairs and confidence, estimating a homography matrix based on the key point pairs, and filtering effective point pairs; Performing gridding difference detection on the chip layout based on the homography matrix and the filtered effective point pairs, inputting the bonding region image into the YOLOv-seg model after optimization to obtain the data of the bonding pad and the solder ball, calculating the deviation proportion, inputting the bonding images of the front batch and the back batch into the bonding type recognition model to output the type and the confidence coefficient, and judging whether to change or not; And outputting results, namely summarizing the difference point data, the solder ball deviation ratio and the judging result, the bonding type identification result and the change judging conclusion, clustering and marking the difference points to generate various visual images, and integrating to form a detection report.
  2. 2. The method for comparing front chip graphic data with back chip graphic data based on a feature matching technology according to claim 1, wherein in the model construction, an improved SuperPoint model construction step is to build a network structure by adopting a deep learning framework, sequentially setting a first convolution layer, a second convolution layer and a linear rectification activation function, newly adding an arbitrary coordinate descriptor extraction function to support descriptor extraction of arbitrary coordinates, configuring a feature descriptor convolution layer to generate feature descriptors, setting a non-maximum suppression radius and descriptor dimension parameters, carrying out normalization processing on the extracted feature descriptors through a feature descriptor L2 normalization formula in a descriptor output stage, inputting a marked chip layout image training set to carry out parameter iteration, and completing construction and optimization, wherein the feature descriptor L2 normalization formula is as follows: , wherein, For the normalized feature descriptor vector, For the original feature descriptor vector, Is the L2 norm of the original feature descriptor vector, For the feature descriptor dimension, the value is 256, Is the first of the original feature descriptor vectors The elements.
  3. 3. The method for comparing front and back chip graphic data based on the feature matching technology according to claim 1 is characterized in that in the model construction, the construction step of the joint matching model is that the improved SuperPoint model is integrated into the joint matching model as a feature extraction module based on configuration parameters of the joint matching model initialized by a deep learning framework, a SuperGlue module is loaded as a feature matching core of the joint matching model, an input image data format, a feature matching threshold and an output parameter type of the joint matching model are defined, computing equipment during reasoning of the joint matching model is set, a paired chip layout image training set is input to perform joint training on the joint matching model, and adaptation parameters between the improved SuperPoint model and the SuperGlue module are optimized, so that the joint matching model outputs an reasoning result containing key points, matching indexes and confidence.
  4. 4. The method for comparing front and back chip graphic data based on the feature matching technology according to claim 1 is characterized in that in the model construction, the steps of optimizing and constructing YOLOv-seg instance segmentation models are that a BoTNet module is inserted between a backbone network of the YOLOv8-seg instance segmentation models and a detection head, the BoTNet module is provided with three convolution units and a sequence structure composed of bottleneck converters, the number of input and output channels of the BoTNet module, the expansion coefficient of a hidden channel, the number of heads of the bottleneck converters and resolution parameters are defined, a labeled bonding pad and a solder ball image training set are input into the YOLOv8-seg instance segmentation models, the training batch size, the iteration round and the learning rate are set, weights of the YOLOv8-seg instance segmentation models are adjusted through back propagation, segmentation accuracy of the YOLOv8-seg instance segmentation models is verified by utilizing a test set, and the YOLOv-seg instance segmentation model construction is completed after the optimization.
  5. 5. The method is characterized in that in the model construction, three types of bonding images of ball bonding, wedge bonding and crescent bonding are collected, an image marking tool is used for marking bonding areas and types in the images, a training set and a test set are divided according to the proportion of 8:2, a bonding type recognition model network structure comprising feature extraction, feature fusion and detection heads is built based on YOLOv frames, the bonding type recognition model training is conducted by the input training set, a confidence coefficient threshold is set based on recognition accuracy of a verification set, the bonding type recognition model is set through generalization capability of the test set, the bonding type recognition model construction is completed through screening of final weights, when the trained bonding type recognition model is used, the bonding area images of the chips in the front batch and the bonding area images of the chips in the back batch are respectively input into the training set, the bonding type recognition model network structure comprising feature extraction, feature fusion and detection heads is built, the confidence coefficient threshold is set when the two types are not consistent, and the two types of the two types are not consistent, and the confidence coefficient threshold is not consistent, and the two types are not consistent are set when the two types are changed, and the confidence coefficient threshold is not consistent.
  6. 6. The method for comparing front and back chip graphic data based on the feature matching technology as claimed in claim 1, wherein in the feature matching, the estimation process of the homography matrix is to convert the effective key point pair output by the joint matching model into a numerical array format, set a reprojection error threshold of a random sampling consistency algorithm, obtain a homography matrix of 3×3 and a corresponding mask through iterative computation, screen out effective inner points in a mapping structure by using the mask, filter unreasonable outer points, and establish a projective transformation relation between a source image and a target image by a homography transformation projection formula, wherein the homography transformation projection formula is as follows: , wherein, 、 Is the projected coordinates of the keypoints in the target image, For a 3 x 3 homography matrix, 、 Is the original coordinates of the keypoints in the source image, Is an element of a homography matrix, The value of (2) is 0-2.
  7. 7. The method for comparing front and rear chip graphic data based on the feature matching technology according to claim 1 is characterized in that in the detection execution, the execution operation of gridding difference detection is that effective interior points are projected by a homography matrix to form corresponding point pairs of a source image and a target image, extremum coordinates of an effective matching area are obtained according to coordinate ranges of the corresponding point pairs, grid control parameters are set to control grid density and sampling interval, uniformly distributed x and y coordinates are generated in the extremum coordinate ranges to form uniform grids covering the effective matching area, grid points are projected to corresponding positions of the target image based on the homography matrix, feature descriptors at the grid points of the source image and at the projection grid points of the target image are respectively extracted, feature differences are quantized by calculating similarity distances of the corresponding grid points of the image through a descriptor similarity measurement formula, a threshold value is set, and difference points larger than the threshold value are screened out, and the descriptor similarity measurement formula is as follows: , wherein, For the similarity distance of the corresponding descriptors of the source image and the target image, For a normalized feature descriptor of a source image grid point, Normalized feature descriptors for corresponding grid points of the target image, For the feature descriptor dimension, Normalized feature descriptor sums for source image grid points, respectively The elements.
  8. 8. The method for comparing front and rear chip pattern data based on feature matching technology as set forth in claim 1, wherein in the detecting execution, the calculation step of the solder ball deviation ratio is to count the total number of valid pixels in the solder ball mask outputted by YOLOv-seg example division model to obtain the total number of solder balls, and to process the solder ball mask and the solder pad mask, the solder ball mask is constructed by the solder ball data outputted by YOLOv-seg example division model, the solder pad mask is constructed by the solder pad data outputted by YOLOv-seg example division model, the total number of valid pixels in the result after the processing is counted to obtain the number of pixels exceeding the solder pad area, and then the solder ball deviation ratio is calculated by a solder ball deviation ratio calculation formula, when the total number exceeds 50%, the solder ball deviation is determined, the solder ball deviation ratio calculation formula is: , wherein, For the solder ball offset ratio, For the number of pixels of the solder ball beyond the pad area, Is the total pixel number of the solder balls.
  9. 9. The method for comparing front chip graphic data and back chip graphic data based on the feature matching technology according to claim 1, wherein in the result output, when clustering and labeling, spatially adjacent difference points are clustered into independent difference areas, each difference area corresponds to a chip layout change type, each difference area is labeled, and the specific position and range of each difference area are clearly labeled.
  10. 10. The method for comparing front chip image data with back chip image data based on the feature matching technology according to claim 1, wherein in the result output, various generated visual images comprise homography change images, detection effective range images, solder ball out-of-pad area images and bonding type labeling images, and difference areas, solder ball deviation parts and bonding type recognition results are presented through image color distinction and identification labeling.

Description

Front and back chip graph data comparison method based on feature matching technology Technical Field The invention relates to the technical field of semiconductor chip manufacturing, in particular to a front and back chip pattern data comparison method based on a feature matching technology. Background Along with the development of the semiconductor technology to the high precision and high density, the chip structure is more complex, and different batches of chips of the same model possibly have differences in terms of layout structure, bonding state and the like due to various reasons such as fluctuation of production equipment precision, fine adjustment of technological parameters, interference of environmental factors and the like, and if the differences are not detected in time, the differences can lead to inconsistent chip performance and reduced reliability, even cause faults of terminal products, so that the accurate comparison of unsealing detection images of the chips of different batches is performed, potential differences are identified, and the method is a key link for guaranteeing the stability of the production quality of the chips, and becomes an important requirement of the semiconductor manufacturing industry. However, in the prior art, aiming at the scheme of chip graphic data comparison, the traditional feature extraction method has some limitations, the lack of standardization processing leads to insufficient matching stability, the difficulty in accurately establishing the corresponding relation between different images, the difference detection mostly adopts a local sampling mode, the subtle difference of an effective matching area is easy to miss, the solder ball deviation assessment depends on manual auxiliary judgment or simple pixel statistics, the precision is insufficient, the bonding type identification does not form complete logic of independent identification-confidence screening-batch comparison, the reliability of type change judgment is low, meanwhile, the prior scheme does not integrate the multi-dimensional detection requirement, and the systematic integration and visual presentation of the multi-dimensional detection result are lacking, so that the integrated comparison of layout difference, solder ball state and bonding type cannot be realized at the same time. Disclosure of Invention The invention aims to make up the defects of the prior art and provides a front and back chip graphic data comparison method based on a feature matching technology, the invention establishes a projection transformation relation between a source image and a target image by constructing an improved SuperPoint model and introducing feature descriptor normalization processing, combining a joint matching model to screen effective key point pairs and utilizing a homography matrix, and then realizing the uniform sampling and feature comparison of the whole region through gridding difference detection, wherein the process is used for specifying the feature extraction standard, strengthening the matching stability, guaranteeing the comprehensiveness of sampling, combining the specific type and range of the clustering marking clear difference region, realizing the accurate positioning and information quantization of the chip layout difference, ensuring that various fine changes can be effectively identified, and providing a reliable technical path for the chip layout consistency detection. The invention provides a method for comparing front and back chip graphic data based on a feature matching technology, which comprises the following specific steps: Collecting opening detection images of different batches of chips of the same model, covering chip layout images and bonding area images, collecting bonding solder ball images and ball key, wedge key and crescent key type images, marking a bonding pad, a solder ball area and bonding types, and dividing a training set and a testing set; Constructing a model, namely constructing an improved SuperPoint model based on the acquired annotation image and the divided training set and test set, constructing a joint matching model by integrating the improved SuperPoint model and the SuperGlue module, embedding BoTNet modules in a YOLOv-seg example segmentation model to complete optimization, constructing a bonding type recognition model based on a YOLOv8 framework, and inputting the training set to complete parameter iterative optimization of each model; Feature matching, namely converting an acquired chip layout image into a specified dimension tensor, inputting a trained improved SuperPoint model to extract a feature subset, inputting the feature subset into a joint matching model to output key point pairs and confidence, estimating a homography matrix based on the key point pairs, and filtering effective point pairs; Performing gridding difference detection on the chip layout based on the homography matrix and the filtered effective point pairs, inputting t