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CN-121999344-A - Integrated storage and calculation signal processing method and system for infrared target detection

CN121999344ACN 121999344 ACN121999344 ACN 121999344ACN-121999344-A

Abstract

The application discloses a method and a system for processing a storage and calculation integrated signal for infrared target detection, and relates to the technical field of low-power-consumption end-side intelligent target detection. The method comprises the steps of S1, receiving real-time infrared image signals of an upper computer by a main control FPGA, carrying out infrared image preprocessing by utilizing an algorithm model, and outputting a preprocessing result to a storage and calculation integrated processing carrier plate, S2, carrying out convolution operation by the storage and calculation integrated processing carrier plate based on the preprocessing result to obtain a convolution calculation result, and S3, collecting the preprocessing result and the convolution calculation result by the main control FPGA and feeding back the result to the upper computer. The technical problem that the traditional computing architecture encounters high energy consumption in executing an intelligent algorithm is solved.

Inventors

  • ZHANG XIAOYANG
  • BAI JIAN
  • LIU XIAOLU

Assignees

  • 北京遥感设备研究所

Dates

Publication Date
20260508
Application Date
20251230

Claims (10)

  1. 1. An integrated signal processing method for intelligent infrared target detection is characterized by comprising the following steps: S1, receiving real-time infrared image signals of an upper computer by a main control FPGA, carrying out infrared image preprocessing by utilizing an algorithm model, and outputting a preprocessing result to a memory and calculation integrated processing carrier plate; S2, based on the pretreatment result, carrying out convolution operation by a storage and calculation integrated treatment carrier plate to obtain a convolution calculation result; and S3, summarizing the preprocessing result and the convolution calculation result by the master control FPGA and feeding the result back to the upper computer.
  2. 2. The method of claim 1, wherein the infrared image preprocessing using an algorithmic model comprises: and executing corresponding operators of an algorithm model input layer, a pooling layer, a full connection layer and an activation function layer by the main control FPGA to obtain a preprocessing result.
  3. 3. The method of claim 1, further comprising, prior to performing a convolution operation on the integrated processing carrier, obtaining a convolution result: Quantizing the weight of the algorithm model into preset three values; And loading the quantized convolution kernel weight into an in-memory computing chip array of the memory-computing integrated processing carrier plate, wherein each in-memory computing unit in the array stores a weight value, and a plurality of in-memory computing units form a convolution kernel.
  4. 4. A method according to claim 3, wherein the convolving by the integrated processing carrier plate to obtain a convolved result comprises: S21, mapping an image window of the preprocessing result to word line input of an in-memory computing chip array, wherein the size of the image window is the same as that of a convolution kernel; S22, calculating the inner product of the convolution kernel and the image window in parallel by a circuit of the internal calculation chip array; S23, calculating an analog inner product through current accumulation, and simultaneously calculating the inner product through all bit lines to complete matrix multiplication; S24, sliding an image window of the preprocessing result, repeating S21-S23, and generating a convolution calculation result.
  5. 5. The method of claim 1, further comprising, prior to said infrared image preprocessing using an algorithmic model: and converting floating point operation of the intelligent algorithm model operator into fixed point number operation by adopting an INT8 linear quantization method.
  6. 6. The method of claim 1, wherein the receiving, by the main control FPGA, the real-time infrared image signal of the host computer, performing the infrared image preprocessing by using the algorithm model, and outputting the preprocessing result to the integrated processing carrier, includes: and a line buffer mechanism is adopted, single-line input is carried out on a single port of the main control FPGA in a pipeline form, and multiple lines of data are output in parallel through caching historical input image data.
  7. 7. The method of claim 1, further comprising, prior to performing a convolution operation by a memory integrated processing carrier based on the preprocessing result, obtaining a convolution calculation result: And receiving the preprocessing result by a cooperative FPGA in the integrated processing carrier plate.
  8. 8. The method of claim 7, further comprising, after the convolving by the integrated processing carrier based on the preprocessing result to obtain a convolved result: And sending the convolution calculation result to a main control FPGA by a cooperative FPGA in the integrated processing carrier plate.
  9. 9. The utility model provides an integrative signal processing system that calculates that deposits towards intelligent infrared target detects which characterized in that includes master control FPGA and deposits integrative processing carrier plate, wherein: The main control FPGA is used for receiving the real-time infrared image of the upper computer, preprocessing the infrared image by utilizing the algorithm model, and sending the preprocessing result to the integrated processing carrier plate for calculation; the integrated processing carrier plate is used for carrying out convolution operation based on the pretreatment result to obtain a convolution calculation result.
  10. 10. The system of claim 9, wherein the integrated processing carrier further comprises a co-FPGA: The collaborative FPGA is used for receiving the preprocessing result and sending the convolution calculation result to the main control FPGA.

Description

Integrated storage and calculation signal processing method and system for infrared target detection Technical Field The application relates to the technical field of low-power consumption end-side intelligent target detection, in particular to a method and a system for processing a storage and calculation integrated signal for infrared target detection. Background The infrared image has the characteristics of all-weather operation, good concealment, less influence of weather and the like, is widely applied in the modern military field, is used as a key technology for military striking, has been paid attention for a long time, and becomes a research focus in the precision guidance field. However, under the strong constraints of space volume and energy consumption of precisely guided missile weapons, the traditional von neumann processing architecture adopted on current missiles cannot meet the requirements of complex environments and the computing power required by infrared target detection in interference combat scenes. Disclosure of Invention The application aims to provide a method for transmitting the convolution calculation result to a main control FPGA, so as to solve the technical problem that the traditional calculation architecture encounters high energy consumption when an intelligent algorithm is executed. In order to achieve the above purpose, the application adopts the following technical scheme: in one aspect, the application provides a method for processing a storage and calculation integrated signal for intelligent infrared target detection, which comprises the following steps: S1, receiving real-time infrared image signals of an upper computer by a main control FPGA, carrying out infrared image preprocessing by utilizing an algorithm model, and outputting a preprocessing result to a memory and calculation integrated processing carrier plate; S2, based on the pretreatment result, carrying out convolution operation by a storage and calculation integrated treatment carrier plate to obtain a convolution calculation result; and S3, summarizing the preprocessing result and the convolution calculation result by the master control FPGA and feeding the result back to the upper computer. On the other hand, the application also provides a system for processing the integrated storage and calculation signal for intelligent infrared target detection, which comprises the following steps: The main control FPGA is used for receiving the real-time infrared image of the upper computer, preprocessing the infrared image by utilizing the algorithm model, and sending the preprocessing result to the integrated processing carrier plate for calculation; the integrated processing carrier plate is used for carrying out convolution operation based on the pretreatment result to obtain a convolution calculation result. Based on the technical scheme, the application can obtain the following technical effects: And the main control FPGA receives the data of the upper computer and performs preprocessing, the integrated processing carrier plate is used for carrying out carrier plate control and convolution calculation, the target detection task is completed, and the detection result is integrated by the main control FPGA and then returned to the upper computer for display. The method is simple and reliable, and meanwhile, based on the integrated memory chip, the energy efficiency of the intelligent detection processing of the end-side equipment for the infrared target is effectively improved, the technical problem that the traditional computing architecture encounters high energy consumption when the intelligent algorithm is executed is solved, the low-power-consumption implementation of the intelligent target detection of the edge equipment end is supported, and ideal processing ideas and hardware platforms are provided for AI application. Drawings FIG. 1 is a schematic flow chart of a method for processing integrated signals for intelligent infrared target detection according to an embodiment of the present application; FIG. 2 is a schematic diagram of in-memory computing chip-side weights and an input mapping scheme according to an embodiment of the present application; FIG. 3 is a schematic diagram of an integrated signal processing system for intelligent infrared target detection according to an embodiment of the present application. Detailed Description The advantages and features of the present application will become more fully apparent from the following description and appended claims, taken in conjunction with the accompanying drawings and detailed description. It should be noted that the drawings are in a very simplified form and are adapted to non-precise proportions, merely for the purpose of facilitating and clearly aiding in the description of embodiments of the application. It should be noted that, in order to clearly illustrate the present application, various embodiments of the present application are speci