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CN-121999706-A - Gate driving circuit, partial brushing control method and display panel

CN121999706ACN 121999706 ACN121999706 ACN 121999706ACN-121999706-A

Abstract

The application belongs to the technical field of display driving, and particularly relates to a gate driving circuit, a local brushing control method and a display panel, wherein an nth-stage gate driving module comprises a level transmission generating unit which is configured to respond to an nth-1-stage level transmission signal and a current-stage level transmission clock signal and output an nth-stage level transmission signal through a current-stage level transmission output end, a driving control unit which is configured to establish driving control voltage on a driving control node according to the nth-stage level transmission signal, and a driving output unit which is configured to respond to the driving control voltage and the current-stage driving clock signal and generate a current-stage gate driving signal.

Inventors

  • LAN TIAN
  • XU PEI

Assignees

  • 惠科股份有限公司

Dates

Publication Date
20260508
Application Date
20260408

Claims (10)

  1. 1. A gate driving circuit comprising N cascaded gate driving modules, wherein an nth stage gate driving module comprises: The level transmission generating unit is connected with the level transmission clock signal line of the current level and the level transmission output end of the n-1 level grid driving module and is configured to respond to the n-1 level transmission signal and the level transmission clock signal of the current level and output the n level transmission signal through the level transmission output end of the current level; The drive control unit is connected with the level transmission output end of the current level and the drive control node and is configured to establish a drive control voltage on the drive control node according to the nth level transmission signal, wherein the amplitude of the drive control voltage is larger than that of the nth level transmission signal; A driving output unit connected to the driving control node and the driving clock signal line of the current stage and configured to generate a gate driving signal of the current stage in response to the driving control voltage and the driving clock signal of the current stage; The drive clock signal line outputs an effective level in a refresh line in a local refresh mode, the drive clock signal line outputs an ineffective level in a non-refresh line in the local refresh mode, and the hierarchical clock signal line and the drive clock signal line are mutually independent signal lines.
  2. 2. The gate driving circuit according to claim 1, wherein the gradation generation unit includes: The control end of the first transistor and the first end of the first transistor are respectively connected with the level transmission output end of the n-1 level grid driving module, and the second end of the first transistor is used as a level transmission control node; the control end of the second transistor is connected with the level transmission control node, the first end of the second transistor is connected with the level transmission clock signal line, and the second end of the second transistor is used as a level transmission output end; the first end of the first capacitor is connected with the level transmission control node, and the second end of the first capacitor is connected with the level transmission output end.
  3. 3. The gate driving circuit according to claim 2, wherein the gradation generation unit further comprises: and the control end of the third transistor is connected with the level transmission output end of the n+1th level grid electrode driving module, the first end of the third transistor is connected with the level transmission control node, and the second end of the third transistor is connected with the low level end.
  4. 4. The gate drive circuit according to claim 1, wherein the drive control unit includes: A control end of the fourth transistor and a first end of the fourth transistor are connected with the level transmission output end, and a second end of the fourth transistor is used as an intermediate control node; A fifth transistor, a control end of which is connected to the intermediate control node, a first end of which is connected to a power supply voltage end, and a second end of which is used as a driving control node; And the first end of the second capacitor is connected with the intermediate control node, and the second end of the second capacitor is connected with the power supply voltage end.
  5. 5. The gate drive circuit according to claim 1, wherein the drive control unit includes: A control end of the fourth transistor and a first end of the fourth transistor are connected with the level transmission output end, and a second end of the fourth transistor is used as an intermediate control node; A fifth transistor, a control end of which is connected to the intermediate control node, a first end of which is connected to a power supply voltage end, and a second end of which is used as a driving control node; and the first end of the second capacitor is connected with the intermediate control node, and the second end of the second capacitor is connected with the driving control node.
  6. 6. The gate driving circuit according to claim 1, wherein the driving output unit includes: A sixth transistor, a control terminal of which is connected to the driving control node, a first terminal of which is connected to the driving clock signal line, and a second terminal of which is a driving output terminal; and the first end of the third capacitor is connected with the driving control node, and the second end of the third capacitor is connected with the driving output end.
  7. 7. The gate driving circuit according to any one of claims 1 to 6, wherein the gate driving module further comprises a pull-down unit comprising: a control end of the seventh transistor is connected with a level transmission output end of the n+i level grid driving module, a first end of the seventh transistor is connected with a driving output end, and a second end of the seventh transistor is connected with a low level end; An eighth transistor, a control terminal of the eighth transistor is connected to the control terminal of the seventh transistor, a first terminal of the eighth transistor is connected to a driving control node, and a second terminal of the eighth transistor is connected to the low level terminal; And a control end of the ninth transistor is connected with the control end of the seventh transistor, a first end of the ninth transistor is connected with the intermediate control node, and a second end of the ninth transistor is connected with the low level end.
  8. 8. A partial brushing control method, applied to the gate driving circuit according to any one of claims 1 to 7, comprising: In the global refresh mode and the local refresh mode, generating a current-stage hierarchical signal in response to a previous-stage hierarchical signal and a current-stage hierarchical clock signal; Establishing a drive control voltage on a drive control node according to the hierarchical signal; In the local refresh mode, the driving clock signal line of the current stage is controlled to output an effective level in a corresponding period of the refresh line, so that the refresh line outputs a gate driving signal of the current stage under the combined action of the driving control voltage and the driving clock signal.
  9. 9. The partial brush control method according to claim 8, the method is characterized in that the office brush control method further comprises the following steps: In the partial refresh mode, the driving clock signal line of the current stage is controlled to output an invalid level in a corresponding period of the non-refresh line, so that the non-refresh line has no gate driving signal output.
  10. 10. A display panel comprising a display area and a non-display area, the display area comprising a plurality of scan lines, characterized in that the non-display area comprises a gate drive circuit according to any one of claims 1-7, a drive output of the gate drive circuit being electrically connected to at least one scan line.

Description

Gate driving circuit, partial brushing control method and display panel Technical Field The disclosure belongs to the technical field of display driving, and particularly relates to a gate driving circuit, a local brush control method and a display panel. Background With the increasing demands of display devices for large size, high resolution and low power consumption, progressive scanning using GOA (GATE DRIVER on Array) technology has become a mainstream driving method. In order to reduce the power consumption of the display device, a display mode of partial refresh is proposed, namely, only scanning is performed in a picture update area instead of refreshing the whole screen, thereby remarkably reducing the power consumption of GOA and driving IC. However, in the GOA circuit of the current local refresh, under the multi-CK architecture, due to the longer time sequence overlapping area between adjacent stage signals, erroneous output is usually generated at the edge of the refresh area, resulting in abnormal display, and the reliability of the local refresh is reduced. Therefore, how to improve the false output of the local refresh edge position is a current urgent problem to be solved. Disclosure of Invention The embodiment of the application provides a gate driving circuit, a local brushing control method and a display panel, which eliminate the problem of false output generated at the edge of a local refreshing area due to overlapping of adjacent stage signal time sequences by decoupling the generation of a stage signal and the output of a gate driving signal, and ensure the accuracy and the boundary definition of picture display. In a first aspect, the application provides a gate driving circuit, which comprises N cascaded gate driving modules, wherein the nth gate driving module comprises a level transmission generating unit which is connected with a level transmission clock signal line of a current level and a level transmission output end of the nth-1 gate driving module and is configured to respond to the N-1 level transmission signal and the level transmission clock signal of the current level and output the nth level transmission signal through the level transmission output end of the current level, a driving control unit which is connected with the level transmission output end of the current level and a driving control node and is configured to establish a driving control voltage on the driving control node according to the nth level transmission signal, wherein the amplitude of the driving control voltage is larger than the amplitude of the nth level transmission signal, a driving output unit which is connected with the driving control node and the driving clock signal line of the current level and is configured to respond to the driving control voltage and the driving clock signal of the current level, a refresh signal line of the current level is generated, the driving control signal line in a local refresh mode is effective, the driving clock signal line is ineffective, and the driving clock signal line is ineffective in the local level and the driving clock signal line is ineffective. Optionally, the level transmission generating unit comprises a first transistor, a second transistor, a first capacitor and a first capacitor, wherein the control end of the first transistor and the first end of the first transistor are respectively connected with the level transmission output end of the n-1 level grid driving module, the second end of the first transistor is used as a level transmission control node, the control end of the second transistor is connected with the level transmission control node, the first end of the second transistor is connected with the level transmission clock signal line, the second end of the second transistor is used as a level transmission output end, the first end of the first capacitor is connected with the level transmission control node, and the second end of the first capacitor is connected with the level transmission output end. Optionally, the level generation unit further comprises a third transistor, wherein the control end of the third transistor is connected with the level transmission output end of the n+1th level grid driving module, the first end of the third transistor is connected with the level transmission control node, and the second end of the third transistor is connected with the low level end. Optionally, the driving control unit comprises a fourth transistor, a fifth transistor, a second capacitor and a second capacitor, wherein the control end of the fourth transistor and the first end of the fourth transistor are connected with the output end of the cascade, the second end of the fourth transistor is used as an intermediate control node, the control end of the fifth transistor is connected with the intermediate control node, the first end of the fifth transistor is connected with a power supply voltage end, the second end of the fifth transi