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CN-121999715-A - 2T1C display driving circuit structure based on two-dimensional transistor and preparation method thereof

CN121999715ACN 121999715 ACN121999715 ACN 121999715ACN-121999715-A

Abstract

The invention provides a 2T1C display driving circuit structure based on a two-dimensional transistor and a preparation method thereof, the method comprises the steps of integrating MoS 2 -FETs and parallel capacitors C ST on a substrate, realizing unit interconnection and array expansion to form a 2T1C array structure, testing the electrical properties of MoS 2 -FETs in the 2T1C array structure to obtain parameters such as threshold voltage, switching ratio, leakage current and saturated on-state current, establishing a time sequence circuit based on a dynamic random access memory DRAM of the 2T1C array structure according to the electrical properties of the MoS 2 -FETs, testing the storage performance of the DRAM of the 2T1C array structure, interconnecting the 2T1C array structure with a Light Emitting Diode (LED) through a peripheral circuit, and testing the driving performance of the 2T1C array structure to the LED. The characteristics of high on-state current and extremely low off-state leakage of the MoS 2 transistor are utilized, and high-speed writing, high driving current output and ultra-long data/current holding time are realized.

Inventors

  • LIU LIWEI
  • ZHOU PENG
  • CHEN LIN
  • Hu Yinglang

Assignees

  • 复旦大学

Dates

Publication Date
20260508
Application Date
20251226

Claims (10)

  1. 1. The preparation method of the 2T1C display driving circuit structure based on the two-dimensional transistor is characterized by comprising the following steps: Integrating two-dimensional transistors MoS 2 -FETs and parallel capacitors C ST on a substrate, and realizing unit interconnection and array expansion to form a 2T1C array structure; Testing the electrical properties of MoS 2 -FETs in the 2T1C array structure to obtain parameters such as threshold voltage, switching ratio, leakage current, saturation on-state current and the like; According to the electrical property of MoS 2 -FETs, a time sequence circuit based on a dynamic random access memory DRAM with a 2T1C array structure is established; Testing the storage performance of the 2T1C array structure DRAM; And interconnecting the 2T1C array structure with the Light Emitting Diode (LED) through a peripheral circuit, and testing the driving performance of the 2T1C array structure on the LED.
  2. 2. The method for manufacturing a 2T1C display driving circuit structure based on a two-dimensional transistor according to claim 1, wherein the two-dimensional transistor MoS 2 -FETs and the parallel capacitor C ST are integrated on a substrate, and cell interconnection and array expansion are implemented, so as to form a 2T1C array structure, which specifically comprises: Depositing Cr/Au electrodes on the SiO 2 /Si substrate as gate electrodes of MoS 2 -FETs and lower electrode plates of C ST , wherein the thickness of the Cr layer is 5nm and the thickness of the Au layer is 15nm; Depositing a HfO 2 film with the thickness of 15nm by an atomic layer deposition device, wherein the HfO 2 film is used as a gate dielectric of MoS 2 -FETs and a dielectric layer of C ST ; Using a reactive ion etching device, selecting a mixed gas of boron trichloride and argon as a carrier gas, selectively etching the HfO 2 film to obtain a through hole structure, and depositing 20nm thick Au in the through hole; Transferring a single-layer MoS 2 film on the surface of the HfO 2 dielectric layer by adopting an organic polymer assisted transfer method, and patterning the MoS 2 film by using RIE equipment; And at the moment, the source end of the T1 is interconnected with the grid electrode of the T2 and the lower polar plate of the C ST to obtain a 2T1C circuit structure, wherein the Cr layer thickness of the Cr/Au electrode is 5nm and the Au layer thickness is 25nm.
  3. 3. The method for manufacturing a 2T1C display driving circuit structure based on a two-dimensional transistor according to claim 2, wherein the 2T1C array structure comprises: Two-dimensional transistors MoS 2 -FETs with back gate structures and one parallel plate capacitor C ST ; The conducting channel of the two-dimensional transistor is a single-layer MoS 2 , the channel length is 3 mu m, and the channel width is 30 mu m; The parallel plate capacitor C ST has a size of 50 μm×50 μm, and the dielectric material is half-oxide, and the thickness of the dielectric layer is 15nm.
  4. 4. A method for manufacturing a 2T1C display driver circuit structure based on two-dimensional transistors according to claim 3, wherein the 2T1C array structure has a dual function operation mode: When the dynamic random access memory works as a dynamic random access memory, T1 is a writing transistor, and T2 is a reading transistor; when operating as an LED display driving circuit, T1 is a switching transistor and T2 is a driving transistor.
  5. 5. The method of manufacturing a 2T1C display driver circuit structure based on two-dimensional transistors according to claim 4, wherein when the 2T1C array structure is operated as a dynamic random access memory, T1 is a write transistor having a drain terminal connected to the data voltage V DATA and a gate terminal connected to the scan voltage V SCAN ; T2 is used as a readout transistor, its drain terminal is connected to the power supply voltage V DD , and the source terminal is commonly grounded to the upper plate of C ST ; In the data writing stage, V DD is set at high level, the scanning voltage V SCAN is set at high level, and the T1 transistor is turned on, at this time, the data voltage V DATA is stored to C ST through T1; In the data reading stage, V DD is set at high level, the scan voltage V SCAN is set at low level, the T1 transistor is turned off, the data voltage stored in C ST turns on T2, and the current flowing through T2 is the read current I READ .
  6. 6. The method for manufacturing a 2T1C display driving circuit structure based on a two-dimensional transistor according to claim 4, wherein the memory performance of the 2T1C array structure DRAM is tested, and the memory performance thereof specifically comprises: In the data writing stage, when writing a data voltage of V DATA =1v through T1, the read voltage of the node a is 0.79V, and after 9s, the voltage of the node a is 0.78V, and the attenuation is 0.01V; In the data writing stage, when a data voltage of V DATA =2v is written through T1, the readout current I READ flowing through T2 is 258.36 μa, and after 9s, I READ is 251.28 μa, and the attenuation is 2.74%; in the data writing stage, when a data voltage of V DATA =2v is written through T1, the readout current I READ flowing through T2 is reduced from 234 μa to 210.9 μa within a holding time of 300s, and the current decay is less than 10%; In the data writing phase, when the data voltages V DATA with different pulse widths are written through T1, the fastest writing speed is 500ns, and the node a can be filled to 91.4% of the saturation voltage.
  7. 7. The method for manufacturing a 2T1C display driver circuit structure based on two-dimensional transistors according to claim 4, wherein when the 2T1C array structure is operated as an LED display driver circuit: T1 is a switching transistor, the drain terminal of which is connected to the data voltage V DATA , and the gate terminal of which is connected to the scan voltage V SCAN ; T2 is used as a driving transistor, the drain end of the driving transistor is connected with a power supply voltage V DD , and the source end of the driving transistor is connected with the anode of the LED through a peripheral circuit; In the data writing stage, V DD is set at low level, the scanning voltage V SCAN is set at high level, and the transistor T1 is turned on; In the light emitting stage, V DD is set at high level, the scanning voltage V SCAN is set at low level, the T1 transistor is turned off, the data voltage stored in C ST turns on T2, and the current flowing through T2 is the LED driving current.
  8. 8. The method for manufacturing a 2T1C display driving circuit structure based on a two-dimensional transistor according to claim 1, wherein the performance of driving the LED by the 2T1C structure comprises: in the data writing stage, after the data voltage V DATA with different pulse amplitudes and the writing frequency of 10kHz is written through T1, the time required by the rising edge of the reading voltage of the node A is 16 mu s, and the falling edge is 4 mu s; In the data writing stage, after the data voltage V DATA with different pulse widths and the writing frequency of 11.52kHz is written through T1, the reading voltage of the node A is basically unchanged.
  9. 9. The method for manufacturing a 2T1C display driving circuit structure based on a two-dimensional transistor according to claim 1, wherein the performance of driving the LED by the 2T1C structure further comprises: in the light emitting stage, when V DD is set at a high level of 2.5V, the driving current I LED flowing through the LED is reduced from 57.33 mu A to 52.13 mu A in the holding time of 100s, and the current is attenuated by 9.1%; In the light emitting stage, the data voltage written into the V DATA through T1 is gradually increased from 2.4V to 3.9V, the maximum driving current I LED flowing through the LED is basically linearly increased, the brightness of the LED is also gradually lightened, and in the continuous lighting process of 20s, the current attenuation of I LED is less than 10%.
  10. 10. A 2T1C display driving circuit structure based on a two-dimensional transistor, characterized in that it is manufactured by adopting a 2T1C display driving circuit structure manufacturing method based on a two-dimensional transistor as described in claims 1-9, comprising: The device comprises a substrate, a bottom electrode layer on the upper surface of the substrate, a dielectric layer covered on the bottom electrode layer, a core functional layer on the dielectric layer, a top electrode layer positioned on the exposed surfaces of the core functional layer and the dielectric layer, and a parallel plate capacitor and a peripheral interconnection interface which are arranged on the substrate.

Description

2T1C display driving circuit structure based on two-dimensional transistor and preparation method thereof Technical Field The invention relates to the technical field of display driving circuits, in particular to a 2T1C display driving circuit structure based on a two-dimensional transistor and a preparation method thereof. Background The 2T1C (Two-Transistor-One-Capacitor) structure is composed of Two transistors T1, T2 and a storage Capacitor C ST, and is widely used as a basic circuit unit for Dynamic Random Access Memory (DRAM) storage and LED display driving systems. Although both are similar in circuit topology, there are significant differences in design goals, performance requirements and operating mechanisms. In the DRAM, a 2T1C structure is used as a binary data access unit, T1 is used as a writing transistor for writing and erasing data, charges are stored in a capacitor C ST in the form of "0" or "1", C ST holds the data voltage and controls the gate potential of T2 after T1 is turned off, and T2 is used as a reading transistor for determining an output state. In display applications, the 2T1C structure acts as an LED active drive circuit unit, T1 acts as a switching transistor to charge the capacitor C ST to a target voltage, and T2 acts as a drive transistor to determine the current to the LED. For both applications, conventional silicon-based DRAM requires periodic refresh (< 64 ms) operations to maintain the stored charge and data voltage, since the charge stored by capacitor C ST is gradually lost through transistor and dielectric leakage currents. In recent years, the construction of 2T1C circuits using oxide semiconductor IGZO-TFTs has exhibited significant advantages in DRAM storage and display driving. First, IGZO has extremely low intrinsic leakage current (as low as 10-20A/μm), significantly better than conventional thin film transistor materials such as a-Si and LTPS. The characteristic enables the 2T1C circuit to have natural advantages in the aspects of long-time node voltage maintenance (> 1000 s) and high durability (erasing times-10 11). In addition, the electron mobility of the IGZO-TFTs is generally up to 30cm 2/V.s, higher driving current output can be realized, and the requirements of OLED, mini/Micro-LED and other display devices on current driving capability can be met. Meanwhile, the IGZO process temperature is low (< 400 ℃) and is highly compatible with the silicon-based back-end process and the flexible substrate, and the excellent large-area uniformity is combined, so that the IGZO process is particularly suitable for array integration of large-size high-resolution panels. However, the amorphous structure of IGZO-TFTs is prone to threshold voltage drift (PBS/NBS) under bias voltage, resulting in drive tube current decay or increased leakage current, which affects pixel brightness uniformity and retention performance, which is particularly pronounced in high current density drive or long-term static retention scenarios. Along with the requirements of VR/AR/MR and other immersive interaction scenes or Micro-LEDs on display equipment with higher integration level, lower power consumption and low time delay, the traditional TFT driving circuit gradually approaches performance limits in the aspects of display resolution, frequency refreshing, system power consumption and the like. The two-dimensional semiconductor material, particularly single-layer molybdenum disulfide (MoS 2), provides possibility for realizing high driving current and long data retention time simultaneously due to the intrinsic advantages of atomic-level thickness, high carrier mobility, extremely high on/off ratio (> 10 8), extremely low off-state leakage current (fA level) and the like. The MoS 2 -FETs driving circuit with a 32 multiplied by 32 matrix is prepared by monolithically integrating a MoS 2 -FETs array with a GaN-based Micro-LED display chip through a BEOL technology for the first time by a professor topic group of Nanjing university Wang Xinran. The two-dimensional material is verified to have application potential in the fields of future micro display screens, vehicle-mounted displays and the like. The method for synthesizing the MoS 2 film by transferring MoS 2 to a flexible PET substrate or directly on a gallium nitride (GaN) epitaxial wafer by using Jong-Hyun Ahn subject group of Korean university of extension achieves the driving of RGB-OLED and micro-LED, and is expected to be used for developing future wearable electronic application. However, the circuit architecture reported above is mainly based on a 1T1D structure, i.e. one MoS 2 -FET drives one light-emitting pixel, and the electric field stability, uniformity, etc. of the two-dimensional transistor affect the LED light-emitting function. Other driving circuit structures, such as 2T1C structures based on MoS 2 -FETs, have also been reported, but functional verification of stable driving of LEDs has been lacking. In summary, the p