CN-121999720-A - Gate drive circuit and display panel

CN121999720ACN 121999720 ACN121999720 ACN 121999720ACN-121999720-A

Abstract

The application belongs to the technical field of display driving, and particularly relates to a grid driving circuit and a display panel, wherein the grid driving circuit comprises N cascaded grid driving units, each grid driving unit comprises a pull-up module, an output module and a charge compensation module, wherein the pull-up module is configured to precharge a driving control node according to an N-i level transmission signal output by an N-i level output module, the output module is configured to output a level transmission signal of a current level and at least two grid driving signals under the action of driving voltage and at least two clock signals on the driving control node, and the charge compensation module is configured to precharge the driving control node to an initial compensation voltage under the action of the N-i level transmission signal, and maintain the driving control node to a target driving voltage under the action of the initial compensation voltage and an external compensation signal in at least two driving signal output periods of the output module when the driving voltage of the driving control node is located in a preset voltage threshold range. The application can improve the stability of the grid driving voltage.

Inventors

QU TAO
CUI JIANYU
LI ZEYAO
LAN TIAN
ZHU XIANFEI
YE LIDAN

Assignees

惠科股份有限公司

Dates

Publication Date: 20260508
Application Date: 20260408

Claims (10)

1. A gate drive circuit comprising N cascaded gate drive units, each gate drive unit comprising: The pull-up module is connected with the drive control node and is configured to precharge the drive control node according to the n-i level transmission signal output by the n-i level output module; The output module is connected with the drive control node and at least two clock signal lines corresponding to the current stage and is configured to output a level transmission signal of the current stage and at least two grid drive signals under the action of the drive voltage on the drive control node and the at least two clock signals; The charge compensation module is connected with the driving control node and the external control device and is configured to be pre-charged to an initial compensation voltage under the action of the n-i level transmission signal, and when the driving voltage of the driving control node is in a preset voltage threshold range, the driving control node is maintained to a target driving voltage under the action of the initial compensation voltage and the external compensation signal in at least two driving signal output periods of the output module.
2. The gate drive circuit of claim 1, wherein the charge compensation module comprises: the pre-charging sub-module is connected with the driving control node and is configured to be pre-charged to an initial compensation voltage under the effect of an n-i level transmission signal output by the n-i level output module; And the maintaining sub-module is connected with the pre-charging sub-module, the external control device and the driving output end of the output module and is configured to maintain the driving control node at the target driving voltage under the actions of the initial compensation voltage, the grid driving signal output by the output module and the external compensation signal in at least two driving signal output periods of the output module when the driving voltage of the driving control node is in the preset voltage threshold range.
3. The gate drive circuit of claim 2, wherein the precharge submodule includes a first transistor, a first capacitor, a second transistor, and a third transistor; The control end of the first transistor is connected with the driving control node, the second end of the first transistor is connected with the first end of the first capacitor, and the control end of the second transistor is connected with the first end of the second transistor; The second end of the first capacitor is connected with the first end of the third transistor and the maintaining submodule respectively; A second end of the second transistor is connected with the driving control node; The control end of the third transistor is connected with the level transmission output end of the n-i level output module, and the second end of the third transistor is connected with the low level end.
4. The gate drive circuit of claim 2, wherein the sustain submodule includes a fourth transistor; The control end of the fourth transistor is connected with the driving output end of the output module, and the first end of the fourth transistor is connected with the external control device.
5. The gate drive circuit of claim 2, wherein the precharge submodule includes a first transistor, a second transistor, a first capacitor, and a third transistor; The control end of the first transistor is respectively connected with the first end of the first transistor, the second end of the second transistor and the first end of the first capacitor, and the second end of the first transistor is connected with the driving control node; the control end of the second transistor is connected with the level transmission output end of the n-i level output module, and the first end of the second transistor is connected with the high level end; the second end of the first capacitor and the first end of the third transistor are connected with the maintenance submodule; The control end of the third transistor is connected with the level transmission output end of the n-i level output module, and the second end of the third transistor is connected with the low level end.
6. The gate drive circuit of claim 2, wherein the sustain submodule includes a fourth transistor, a second capacitor, a fifth transistor, and a sixth transistor; The control end of the fourth transistor is connected with the driving output end of the output module, the first end of the fourth transistor is connected with the high level end, and the second end of the fourth transistor is connected with the pre-charging sub-module and the first end of the second capacitor; The second end of the second capacitor is connected with the first end of the fifth transistor and the second end of the sixth transistor; The first control end of the fifth transistor is connected with the driving output end of the output module, the second control end of the fifth transistor is connected with the output end of the noise reduction control signal, and the second end of the fifth transistor is connected with the low level end; The control end of the sixth transistor is connected with the driving output end of the output module, and the first end of the sixth transistor is connected with the external control device.
7. The gate drive circuit of claim 6, wherein the gate drive unit further comprises: And the noise reduction module is respectively connected with the driving control node and the second control end of the fifth transistor and is configured to generate the noise reduction control signal according to the driving voltage of the driving control node.
8. The gate drive circuit of claim 1, wherein the output module comprises a seventh transistor, at least two eighth transistors, a third capacitor, and at least two fourth capacitors; The control end of the seventh transistor, the first end of the third capacitor, the control end of each eighth transistor and the first end of each fourth capacitor are connected to the driving control node, the first end of the seventh transistor is connected with a clock signal line, and the second end of the seventh transistor is connected with the second end of the third capacitor; The first end of each eighth transistor is connected with one clock signal line, and the second end of each eighth transistor is connected with the second end of the corresponding fourth capacitor.
9. The gate drive circuit according to claim 2, wherein the gate drive unit further comprises: the detection module is respectively connected with the driving control node and the external control device and is configured to detect the driving voltage of the driving control node and output the driving voltage to the external control device so that the external controller can generate the external compensation signal according to the driving voltage of the driving control node.
10. A display panel comprising a display area and a non-display area, the display area comprising a plurality of scan lines, characterized in that the non-display area comprises a gate drive circuit according to any one of claims 1-9, an output module of the gate drive circuit being connected to at least one of the scan lines.

Description

Gate drive circuit and display panel Technical Field The application belongs to the technical field of display, and particularly relates to a gate driving circuit and a display panel. Background With the development of high resolution and high refresh rate display panels, a scanning driving (GATE DRIVER on Left, GDL) circuit is widely used in Active-matrix organic light Emitting diodes (AMOLED) and electronic paper display devices. In order to realize a narrow frame design, a plurality of grid driving signals are commonly output to share one driving control node for control, so that wiring is simplified and load is reduced. However, this wiring will cause leakage of the driving control node, and the output gate driving voltage will be unstable. Disclosure of Invention The application provides a gate driving circuit and a display panel, which solve the problem of unstable gate driving voltage. The application provides a grid driving circuit, which comprises N cascaded grid driving units, wherein each grid driving unit comprises a pull-up module, an output module and a charge compensation module, the pull-up module is connected with a driving control node and is configured to precharge the driving control node according to an N-i level transmission signal output by an N-i level output module, the output module is connected with at least two clock signal lines corresponding to the driving control node and a current level and is configured to output the level transmission signal of the current level and at least two grid driving signals under the action of a driving voltage and at least two clock signals on the driving control node, the charge compensation module is connected with the driving control node and an external control device and is configured to precharge to an initial compensation voltage under the action of the N-i level transmission signal and maintain the driving control node to a target driving voltage under the action of the initial compensation voltage and an external compensation signal in at least two driving signal output periods of the output module when the driving voltage of the driving control node is in a preset voltage threshold range. Optionally, the charge compensation module comprises a pre-charging sub-module connected with the drive control node and configured to pre-charge to an initial compensation voltage under the action of an n-i level transmission signal output by the n-i level output module, and a maintaining sub-module connected with the pre-charging sub-module, the external control device and the drive output end of the output module and configured to maintain the target drive voltage by the drive control node under the action of the initial compensation voltage, a gate drive signal output by the output module and the external compensation signal in at least two drive signal output periods of the output module when the drive voltage of the drive control node is within the preset voltage threshold range. Optionally, the pre-charging submodule comprises a first transistor, a first capacitor, a second transistor and a third transistor, wherein a control end of the first transistor, a first end of the first transistor is connected with the driving control node, a second end of the first transistor is connected with the first end of the first capacitor, a control end of the second transistor is connected with the first end of the second transistor, a second end of the first capacitor is respectively connected with the first end of the third transistor and the maintaining submodule, a second end of the second transistor is connected with the driving control node, a control end of the third transistor is connected with a level transmission output end of the n-i stage output module, and a second end of the third transistor is connected with a low level end. Optionally, the maintaining sub-module comprises a fourth transistor, wherein the control end of the fourth transistor is connected with the driving output end of the output module, and the first end of the fourth transistor is connected with the external control device. Optionally, the pre-charging submodule comprises a first transistor, a second transistor, a first capacitor and a third transistor, wherein the control end of the first transistor is connected with the first end of the first transistor, the second end of the second transistor is connected with the first end of the first capacitor, the second end of the first transistor is connected with the driving control node, the control end of the second transistor is connected with the level transmission output end of the n-i level output module, the first end of the second transistor is connected with the high level end, the second end of the first capacitor and the first end of the third transistor are connected with the maintaining submodule, the control end of the third transistor is connected with the level transmission output end of the n-i level output module, and