CN-121999722-A - Display substrate and display device

Abstract

A display substrate and a display device, wherein the display substrate comprises a gate driving circuit and a clock signal line group, the clock signal line group comprises a plurality of clock signal lines, the gate driving circuit comprises a plurality of cascaded shift registers, at least one stage of shift registers in the plurality of cascaded shift registers is electrically connected with at least one clock signal line in the plurality of clock signal lines, the at least one stage of shift registers in the plurality of cascaded shift registers comprises at least one output transistor, and orthographic projection of the at least one clock signal line in the plurality of clock signal lines on a substrate and orthographic projection of the at least one output transistor in the at least one stage of shift registers in the plurality of cascaded shift registers at least partially overlap.

Inventors

• LI TING
• DONG XIANGDAN
• HUANG YAO
• YAN JUN
• WANG QIWEI
• GAO WENHUI
• CHAI MINGZHI
• LI MENG
• LIU MIAO

Assignees

• 京东方科技集团股份有限公司
• 成都京东方光电科技有限公司
• 北京京东方技术开发有限公司

Dates

Publication Date

20260508

Application Date

20241106

Claims (20)

1. 1. A display substrate having a display region and a non-display region located at least one side of the display region, wherein the display substrate comprises a substrate, a gate driving circuit and a clock signal line group, wherein the gate driving circuit and the clock signal line group are arranged on the substrate and located in the non-display region, the clock signal line group comprises a plurality of clock signal lines, the gate driving circuit comprises a plurality of cascaded shift registers, at least one stage of shift registers in the cascaded shift registers is electrically connected with at least one clock signal line in the plurality of clock signal lines, and at least one stage of shift registers in the cascaded shift registers comprises at least one output transistor; the orthographic projection of at least one clock signal line of the plurality of clock signal lines on the substrate at least partially overlaps with the orthographic projection of at least one output transistor of at least one stage of shift register of the plurality of cascaded shift registers on the substrate.
2. 2. The display substrate of claim 1, wherein the at least one output transistor comprises a fourth transistor and a fifth transistor, wherein a second pole of the fourth transistor and a second pole of the fifth transistor are electrically connected to a signal output terminal, respectively, and a first pole of the fifth transistor is electrically connected to a first clock signal terminal; The plurality of clock signal lines includes a first clock signal line and a second clock signal line, at least a portion of at least one of the first clock signal line and the second clock signal line extending in a second direction; The first clock signal end of at least one stage of shift register is electrically connected with one of the first clock signal line and the second clock signal line, and the clock signal lines connected with the first clock signal ends of adjacent shift registers are different; The orthographic projection of at least one of the first clock signal line and the second clock signal line on the substrate at least partially overlaps with the orthographic projection of at least one of the fourth transistor and the fifth transistor in the at least one stage of shift register on the substrate, respectively.
3. 3. The display substrate of claim 2, wherein the at least one stage of shift register further comprises a first transistor, a second transistor, a third transistor, and a seventh transistor, wherein the control electrode of the first transistor, the first electrode of the second transistor, and the control electrode of the third transistor are electrically connected to the second clock signal terminal, respectively, and the control electrode of the seventh transistor is electrically connected to the third clock signal terminal; The plurality of clock signal lines further includes a third clock signal line and a fourth clock signal line, at least a portion of at least one of the third clock signal line and the fourth clock signal line extending in a second direction; The second clock signal end of at least one stage of shift register is electrically connected with one of the third clock signal wire and the fourth clock signal wire, the third clock signal end of at least one stage of shift register is electrically connected with the other of the third clock signal wire and the fourth clock signal wire, the second clock signal ends of the shift registers of adjacent stages are connected with different signal wires, the third clock signal ends of the shift registers of adjacent stages are connected with different signal wires, The orthographic projection of at least one of the third clock signal line and the fourth clock signal line on the substrate is positioned at one side of the orthographic projection of at least one of the first clock signal line and the second clock signal line on the substrate, which is far away from the display area.
4. 4. The display substrate according to claim 3, further comprising a power signal line group disposed on the base and located in the non-display region, the at least one stage of shift register further comprising an eighth transistor, a first electrode of the third transistor and a control electrode of the eighth transistor being electrically connected to a first power supply terminal, respectively; The power signal line group comprises a first power line, a second power line and a first power line, wherein at least part of the first power line extends along a second direction, and a first power end of at least one stage of shift register is electrically connected with the first power line; The orthographic projection of the first power line on the substrate is located between the orthographic projection of at least one of the first clock signal line and the second clock signal line on the substrate and the orthographic projection of at least one of the third clock signal line and the fourth clock signal line on the substrate, and at least partially overlaps with the orthographic projection of at least one transistor in the at least one stage of shift register on the substrate.
5. 5. The display substrate according to claim 4, wherein a first pole of a fourth transistor in the at least one stage of shift registers is electrically connected to the second power supply terminal; The power signal line group further comprises a second power line, at least part of the second power line extends along a second direction, and a second power end of the at least one stage of shift register is electrically connected with the second power line; the orthographic projection of the second power line on the substrate is positioned on one side, close to the display area, of the orthographic projection of at least one signal line of the first clock signal line and the second clock signal line on the substrate.
6. 6. The display substrate of claim 5, wherein the at least one stage of shift register further comprises a sixth transistor having a first electrode electrically connected to the third power supply terminal; The power signal line group further comprises a third power line, at least part of the third power line extends along the second direction, and a third power end of the at least one stage of shift register is electrically connected with the third power line; the orthographic projection of the third power line on the substrate is positioned between the orthographic projection of at least one of the third clock signal line and the fourth clock signal line on the substrate and the orthographic projection of the first power line on the substrate.
7. 7. A display substrate according to claim 3 or 6, wherein a first pole of a first transistor in the at least one stage of shift register is electrically connected to the signal input terminal; The display substrate also comprises an initial signal line which is arranged on the base and is positioned in the non-display area, wherein the initial signal line at least partially extends along a second direction, and a signal input end of at least one stage of shift register is electrically connected with the initial signal line; The orthographic projection of the initial signal line on the substrate is positioned on one side of the orthographic projection of at least one signal line of the third clock signal line and the fourth clock signal line on the substrate, which is far away from the display area.
8. 8. The display substrate according to claim 1, wherein the signal lines to which the at least one stage of shift registers are connected include a first clock signal line, a second clock signal line, and a first power supply line; The signal lines connected with the at least one stage of shift register further comprise at least one signal line of a first signal line and a second signal line, wherein the first signal line is a signal line which at least partially overlaps with the orthographic projection of at least one transistor in the at least one stage of shift register on a substrate in the third clock signal line, the fourth clock signal line, the second power line and the third power line, and the signal line which does not have an overlapping area with the orthographic projection of at least one transistor in the at least one stage of shift register on the substrate in the third clock signal line, the fourth clock signal line, the second power line and the third power line.
9. 9. The display substrate of claim 8, further comprising a circuit structure layer disposed on the base, the circuit structure layer comprising a first conductive layer, a second conductive layer, a semiconductor layer, a third conductive layer, a fourth conductive layer, and a fifth conductive layer; The first clock signal line, the second clock signal line and the first signal line are positioned on a fifth conductive layer, and the first power line and the initial signal line are positioned on a fourth conductive layer; the second signal line comprises a first connecting line and a second connecting line which are connected with each other, wherein the orthographic projection of the first connecting line positioned on the same signal line on the substrate at least partially overlaps with the orthographic projection of the second connecting line on the substrate; The first connecting wire of at least one second signal wire is positioned on the fourth conductive layer, and the second connecting wire of at least one second signal wire is positioned on the fifth conductive layer.
10. 10. The display substrate of claim 8, further comprising a circuit structure layer disposed on the base, the circuit structure layer comprising a first conductive layer, a second conductive layer, a semiconductor layer, a third conductive layer, a fourth conductive layer, a fifth conductive layer, and a sixth conductive layer; The initial signal line and the first power line are positioned on a fourth conductive layer, at least one of the first clock signal line, the second clock signal line and the first signal line comprises a third connecting line and a fourth connecting line which are connected with each other, the orthographic projection of the third connecting line positioned on the same signal line on a substrate is at least partially overlapped with the orthographic projection of the fourth connecting line on the substrate, the third connecting line of at least one signal line is positioned on a fifth conductive layer, and the fourth connecting line of at least one signal line is positioned on a sixth conductive layer; The second signal line comprises a fifth connecting line, a sixth connecting line and a seventh connecting line which are connected with each other, orthographic projections of at least two connecting lines of the fifth connecting line, the sixth connecting line and the seventh connecting line which are positioned on the same signal line on a substrate are at least partially overlapped, the fifth connecting line of at least one signal line is positioned on the fourth conductive layer, the sixth connecting line of at least one signal line is positioned on the fifth conductive layer, and the seventh connecting line of at least one signal line is positioned on the sixth conductive layer.
11. 11. The display substrate according to claim 9 or 10, wherein the at least one stage of shift register comprises a plurality of transistors, at least one of the plurality of transistors being an N-type transistor, the at least one of the plurality of transistors comprising a first control electrode and a second control electrode connected to each other; The first control electrode of the at least one transistor is positioned on a side of the active pattern of the at least one transistor close to the substrate, and the second control electrode of the at least one transistor is positioned on a side of the active pattern of the at least one transistor away from the substrate, and the orthographic projection of the first control electrode of the at least one transistor on the substrate at least partially overlaps with the orthographic projection of the second control electrode of the at least one transistor on the substrate.
12. 12. The display substrate of claim 11, wherein a first control electrode of at least one transistor is located in the second conductive layer, a second control electrode of at least one transistor is located in the third conductive layer, and an active pattern of at least one transistor is located in the semiconductor layer; the semiconductor layer is a metal oxide layer.
13. 13. The display substrate of claim 11, further comprising a plurality of first signal connection lines and a plurality of second signal connection lines, at least a portion of at least one of the plurality of first signal connection lines extending in a first direction, at least a portion of at least one of the plurality of second signal connection lines extending in a first direction, the first direction and the second direction intersecting; At least one first signal connection line is electrically connected with at least one electrode of a first control electrode and a second control electrode of a first transistor, at least one electrode of a control electrode and a second control electrode of a third transistor and one signal line of the third clock signal line and the fourth clock signal line respectively, and at least one second signal connection line is electrically connected with one electrode of a first control electrode and a second control electrode of a seventh transistor and the other signal line of the third clock signal line and the fourth clock signal line respectively; at least one of the first signal connection line and the second signal connection line is located in the first conductive layer or the second conductive layer.
14. 14. The display substrate of claim 11, further comprising a plurality of connection vias disposed on the base and located in the non-display area; the number of the connecting through holes exposing the first control electrode of the at least one transistor is at least one, and the number of the connecting through holes exposing the second control electrode of the at least one transistor is at least one.
15. 15. The display substrate of claim 14, wherein the at least one stage of shift register further comprises a second capacitor, a first plate of the second capacitor is electrically connected with the control electrode of the fifth transistor, a second plate of the second capacitor is electrically connected with the signal output terminal, and the plurality of connection vias comprise a first connection via, a second connection via, a third connection via, and a fourth connection via; The first connection via hole and the second connection via hole expose a first control electrode of a fifth transistor, the second connection via hole is positioned at one side of the first connection via hole, which is close to the display area, the third connection via hole and the fourth connection via hole expose a second control electrode of the fifth transistor, and the fourth connection via hole is positioned at one side of the third connection via hole, which is close to the display area; for at least one stage of shift register, the orthographic projection of the first connection via and the third connection via on the substrate is located in the orthographic projection range of the second capacitor on the substrate.
16. 16. The display substrate according to claim 15, wherein the second control electrode of the fifth transistor comprises a first connection section and a plurality of branch sections, the first connection section extending in the second direction, at least one of the plurality of branch sections extending in the first direction, the at least one of the plurality of branch sections being located on a side of the first connection section near the display area and electrically connected to the first connection section; For at least one stage of shift register, the orthographic projection of the first connection section on the substrate is located in the orthographic projection range of the second capacitor on the substrate, the third connection via exposes the first connection section, and the fourth connection via exposes one end of one of the plurality of branch sections far away from the first connection section.
17. 17. The display substrate of claim 16, wherein the second control electrode of the fifth transistor further comprises a second connection segment extending in a second direction; The second connecting section is positioned at one side of the plurality of branch sections close to the display area and is connected with at least one branch section in the plurality of branch sections.
18. 18. The display substrate of claim 11, further comprising a plurality of first dummy structures, at least one of the plurality of first dummy structures being disposed on the same layer as an active pattern of at least one transistor in at least one stage of shift register; the distance between the orthographic projection of at least one first dummy structure of the plurality of first dummy structures on the substrate and the orthographic projection of at least one structure of the active pattern, the first control electrode and the second control electrode of at least one transistor positioned in the at least one stage of shift register is greater than 2 micrometers.
19. 19. The display substrate of claim 18, wherein an orthographic projection of at least one of the plurality of first dummy structures on the substrate at least partially overlaps with an orthographic projection of at least one of the third clock signal line, the fourth clock signal line, and the third power line on the substrate and is electrically connected to at least one of the third clock signal line, the fourth clock signal line, and the third power line.
20. 20. The display substrate of claim 18, further comprising a plurality of second dummy structures, wherein an orthographic projection of at least one of the plurality of second dummy structures on the substrate does not overlap with an orthographic projection of a signal line connected to the first and second electrodes and the at least one stage shift register, the active pattern of the at least one transistor, the first control electrode, the second control electrode, the first and second electrodes, and the at least one stage shift register on the substrate; the second dummy structure is located in at least one of the first conductive layer, the second conductive layer, and the third conductive layer.

Description

Display substrate and display device Technical Field The present disclosure relates to the field of display technologies, but is not limited to, and in particular, to a display substrate and a display device. Background Organic LIGHT EMITTING Diode (OLED) devices, quantum-dot LIGHT EMITTING Diode devices and liquid crystal display devices are all luminous display devices, and have the advantages of self-luminescence, wide viewing angle, high contrast, low power consumption, extremely high reaction speed, light weight, flexibility, low cost and the like. With the continuous development of Display technology, a Flexible Display device (Flexible Display) with signal control by a thin film transistor (Thin Film Transistor, abbreviated as TFT) has become a mainstream product in the current Display field. Disclosure of Invention The following is a summary of the subject matter described in detail herein. This summary is not intended to limit the scope of the claims. In a first aspect, the present disclosure provides a display substrate having a display region and a non-display region located at least one side of the display region, the display substrate including a base, and a gate driving circuit and a clock signal line group disposed on the base and located at the non-display region, the clock signal line group including a plurality of clock signal lines, the gate driving circuit including a plurality of cascaded shift registers, at least one stage of the plurality of cascaded shift registers being electrically connected to at least one clock signal line of the plurality of clock signal lines, at least one stage of the plurality of cascaded shift registers including at least one output transistor; the orthographic projection of at least one clock signal line of the plurality of clock signal lines on the substrate at least partially overlaps with the orthographic projection of at least one output transistor of at least one stage of shift register of the plurality of cascaded shift registers on the substrate. In an exemplary embodiment, the at least one output transistor includes a fourth transistor and a fifth transistor, wherein a second pole of the fourth transistor and a second pole of the fifth transistor are electrically connected to a signal output terminal, respectively, and a first pole of the fifth transistor is electrically connected to a first clock signal terminal; The plurality of clock signal lines includes a first clock signal line and a second clock signal line, at least a portion of at least one of the first clock signal line and the second clock signal line extending in a second direction; The first clock signal end of at least one stage of shift register is electrically connected with one of the first clock signal line and the second clock signal line, and the clock signal lines connected with the first clock signal ends of adjacent shift registers are different; The orthographic projection of at least one of the first clock signal line and the second clock signal line on the substrate at least partially overlaps with the orthographic projection of at least one of the fourth transistor and the fifth transistor in the at least one stage of shift register on the substrate, respectively. In an exemplary embodiment, the at least one stage shift register further includes a first transistor, a second transistor, a third transistor, and a seventh transistor, wherein a control electrode of the first transistor, a first electrode of the second transistor, and a control electrode of the third transistor are electrically connected to the second clock signal terminal, respectively, and a control electrode of the seventh transistor is electrically connected to the third clock signal terminal; The plurality of clock signal lines further includes a third clock signal line and a fourth clock signal line, at least a portion of at least one of the third clock signal line and the fourth clock signal line extending in a second direction; The second clock signal end of at least one stage of shift register is electrically connected with one of the third clock signal wire and the fourth clock signal wire, the third clock signal end of at least one stage of shift register is electrically connected with the other of the third clock signal wire and the fourth clock signal wire, the second clock signal ends of the shift registers of adjacent stages are connected with different signal wires, the third clock signal ends of the shift registers of adjacent stages are connected with different signal wires, The orthographic projection of at least one of the third clock signal line and the fourth clock signal line on the substrate is positioned at one side of the orthographic projection of at least one of the first clock signal line and the second clock signal line on the substrate, which is far away from the display area. In an exemplary embodiment, the display device further comprises a power signal line group arranged on th