CN-121999723-A - Processor, display device and electronic device

CN121999723ACN 121999723 ACN121999723 ACN 121999723ACN-121999723-A

Abstract

Display device, processor and electronic device. The display device includes a pixel unit including pixels each connected to a corresponding one of data lines, a corresponding one of gate lines, and a corresponding one of light emission control lines, a data driver outputting a data voltage through output lines, a data distribution circuit connecting each of the output lines to odd-numbered data lines during a first sub-frame period and connecting each of the output lines to even-numbered data lines during a second sub-frame period, a first gate driver sequentially outputting a first gate signal to each of the first gate lines among the gate lines during the first sub-frame period, a second gate driver sequentially outputting a second gate signal to each of the second gate lines among the gate lines during the second sub-frame period, and a light emission control driver dividing the light emission control lines into four groups and outputting the light emission control signals in units of groups.

Inventors

Pu Shihe

Assignees

三星显示有限公司

Dates

Publication Date: 20260508
Application Date: 20251104
Priority Date: 20241104

Claims (15)

1. A display device, wherein the display device comprises: A pixel unit including a plurality of pixels, each of the plurality of pixels being connected to a corresponding data line among the plurality of data lines, a corresponding gate line among the plurality of gate lines, and a corresponding light emission control line among the plurality of light emission control lines; a data driver outputting a data voltage through an output line; a data distribution circuit that connects each of the plurality of output lines to one of a corresponding pair of the plurality of data lines in response to a first control signal during a first sub-frame period, and connects each of the plurality of output lines to the other of the corresponding pair of data lines in response to a second control signal during a second sub-frame period; A first gate driver sequentially outputting a first gate signal to each of a plurality of first gate lines among the plurality of gate lines during the first sub-frame period; A second gate driver sequentially outputting a second gate signal to each of a plurality of second gate lines among the plurality of gate lines during the second sub-frame period, and And a light emission control driver dividing the plurality of light emission control lines into four groups and outputting light emission control signals in units of groups.
2. The display device according to claim 1, wherein the data distribution circuit connects each of the plurality of output lines to an odd-numbered data line among the corresponding pair of data lines during the first sub-frame period, and connects each of the plurality of output lines to an even-numbered data line among the corresponding pair of data lines during the second sub-frame period.
3. The display device according to claim 2, wherein, A plurality of pixels connected to the odd-numbered data lines among the plurality of pixels are respectively connected to the plurality of first gate lines, and A plurality of pixels connected to the even-numbered data lines among the plurality of pixels are connected to the plurality of second gate lines, respectively.
4. The display device according to claim 1, wherein, The data distribution circuit connects each of the odd-numbered output lines of the plurality of output lines to the odd-numbered data line of the corresponding pair of data lines during the first sub-frame period, and connects each of the even-numbered output lines of the plurality of output lines to the even-numbered data line of the corresponding pair of data lines, and The data distribution circuit connects each of the odd-numbered output lines among the plurality of output lines to the even-numbered data line among the corresponding pair of data lines during the second sub-frame period, and connects each of the even-numbered output lines among the plurality of output lines to the odd-numbered data line among the corresponding pair of data lines.
5. The display device according to claim 1, wherein, The pixel unit includes first and second pixels respectively connected to odd-numbered data lines among the corresponding pair of data lines and alternately arranged in a column direction, and third pixels respectively connected to even-numbered data lines among the corresponding pair of data lines and repeatedly arranged in the column direction, and The first pixel, the second pixel, and the third pixel respectively emit light of different colors.
6. The display device according to claim 5, wherein the data driver alternately outputs a first color data voltage and a second color data voltage to each of the plurality of output lines in synchronization with an output timing of the first gate signal during the first sub-frame period, and outputs a third color data voltage to each of the plurality of output lines in synchronization with an output timing of the second gate signal during the second sub-frame period.
7. The display device according to claim 5, wherein, The data driver alternately outputs a first color data voltage and a second color data voltage to each of odd-numbered output lines among the plurality of output lines during the first sub-frame period in synchronization with an output timing of the first gate signal, and outputs a third color data voltage to each of even-numbered output lines among the plurality of output lines in synchronization with the output timing of the first gate signal, an The data driver outputs the third color data voltage to each of the odd-numbered output lines among the plurality of output lines in synchronization with an output timing of the second gate signal during the second sub-frame period, and alternately outputs the first color data voltage and the second color data voltage to each of the even-numbered output lines among the plurality of output lines in synchronization with the output timing of the second gate signal.
8. The display device according to claim 1, wherein, The first gate driver sequentially outputs the first gate signal to each of the plurality of first gate lines in synchronization with an output timing of the first control signal during the first sub-frame period, and The second gate driver sequentially outputs the second gate signal to each of the plurality of second gate lines in synchronization with an output timing of the second control signal during the second sub-frame period.
9. The display device of claim 1, wherein the light emission control driver outputs the light emission control signal in synchronization with an output timing of a first light emission control clock signal and an output timing of a second light emission control clock signal delayed from the first light emission control clock signal by a preset interval, An odd-numbered light emission control signal among the light emission control signals is output in synchronization with the output timing of the first light emission control clock signal, and An even-numbered light emission control signal among the light emission control signals is output in synchronization with the output timing of the second light emission control clock signal.
10. The display device of claim 1, wherein the light emission control driver operates once during the first sub-frame period and once during the second sub-frame period, The light emission control driver includes a plurality of light emission control stages connected to each other in a subordinate manner, and Each of the plurality of light emission control stages is connected to a corresponding group of four light emission control lines among the plurality of light emission control lines to simultaneously supply a corresponding light emission control signal among the light emission control signals to the group of four light emission control lines.
11. A processor, wherein the processor comprises: a graphic memory; An input circuit that receives an image signal and converts the image signal to generate image data; A first data processing circuit for storing the image data in the graphic memory according to the input order, and A second data processing circuit that reads a plurality of pieces of first sub data corresponding to a plurality of pixels driven during a first sub frame period from the image data stored in the graphic memory and outputs the read pieces of first sub data to an output channel, and reads a plurality of pieces of second sub data corresponding to a plurality of pixels driven during a second sub frame period and outputs the read pieces of second sub data to the output channel.
12. The processor of claim 11, wherein, The first data processing circuit stores the image data in the graphics memory during a first period, The second data processing circuit reads the plurality of first sub-data and the plurality of second sub-data during a second period and outputs the plurality of first sub-data read out and the plurality of second sub-data read out to the output channel, and A portion of the first period overlaps the second period.
13. The processor of claim 11, wherein, The image data comprising a plurality of pieces of pixel pair data, each of the plurality of pieces of pixel pair data comprising two pieces of sub-data, Wherein the second data processing circuit reads a plurality of odd-numbered sub-data from the plurality of pixel pair data during the first sub-frame period and outputs the read plurality of odd-numbered sub-data to the output channel, and The second data processing circuit reads a plurality of even-numbered sub-data from the plurality of pixel pair data during the second sub-frame period and outputs the read plurality of even-numbered sub-data to the output channel, or Wherein the second data processing circuit reads a plurality of odd-numbered sub-data from a plurality of pixel-to-data of odd numbers among the plurality of pixel-to-data during the first sub-frame period, reads a plurality of even-numbered sub-data from a plurality of pixel-to-data of even numbers among the plurality of pixel-to-data, and outputs the read plurality of even-numbered sub-data to the output channel, and The second data processing circuit reads a plurality of even-numbered sub-data from the odd-numbered pixel pair data among the plurality of pixel pair data during the second sub-frame period, reads a plurality of odd-numbered sub-data from the even-numbered pixel pair data among the plurality of pixel pair data, and outputs the read plurality of odd-numbered sub-data to the output channel.
14. An electronic device, wherein the electronic device comprises: Display module, and A processor for controlling the display module, Wherein the processor comprises: a graphic memory; An input circuit that receives an image signal and converts the image signal to generate image data; A first data processing circuit for storing the image data in the graphic memory according to the input order, and A second data processing circuit that reads a plurality of pieces of first sub data corresponding to a plurality of pixels driven during a first sub frame period from the image data stored in the graphic memory and outputs the read pieces of first sub data to an output channel, and reads a plurality of pieces of second sub data corresponding to a plurality of pixels driven during a second sub frame period and outputs the read pieces of second sub data to the output channel.
15. The electronic device of claim 14, wherein the display module comprises: A pixel unit including a plurality of pixels, each of the plurality of pixels being connected to a corresponding data line among the plurality of data lines, a corresponding gate line among the plurality of gate lines, and a corresponding light emission control line among the plurality of light emission control lines; a data driver outputting a data voltage through an output line; The output line is connected to the data driver; a data distribution circuit that connects each of the plurality of output lines to one of a corresponding pair of the plurality of data lines in response to a first control signal during a first sub-frame period, and connects each of the plurality of output lines to the other of the corresponding pair of data lines in response to a second control signal during a second sub-frame period; A first gate driver sequentially outputting a first gate signal to each of a plurality of first gate lines among the plurality of gate lines during the first sub-frame period; A second gate driver sequentially outputting a second gate signal to each of a plurality of second gate lines among the plurality of gate lines during the second sub-frame period, and A light emission control driver dividing the plurality of light emission control lines into four groups and outputting light emission control signals in units of groups, Wherein the data distribution circuit connects each of the plurality of output lines to an odd-numbered data line of the corresponding pair of data lines during the first sub-frame period and connects each of the plurality of output lines to an even-numbered data line of the corresponding pair of data lines during the second sub-frame period, or Wherein the data distribution circuit connects each of the odd-numbered output lines of the plurality of output lines to the odd-numbered data line of the corresponding pair of data lines during the first sub-frame period, and connects each of the even-numbered output lines of the plurality of output lines to the even-numbered data line of the corresponding pair of data lines, and The data distribution circuit connects each of the odd-numbered output lines among the plurality of output lines to the even-numbered data line among the corresponding pair of data lines during the second sub-frame period, and connects each of the even-numbered output lines among the plurality of output lines to the odd-numbered data line among the corresponding pair of data lines.

Description

Processor, display device and electronic device Cross Reference to Related Applications The present application claims priority and ownership of korean patent application No. 10-2024-0154710, filed on month 4 of 2024, 11, the entire contents of which are incorporated herein by reference. Technical Field One or more embodiments relate to a processor, a display device including the processor, and an electronic device including the processor. Background The display device includes a plurality of gate lines, a plurality of data lines, and a plurality of pixels positioned at intersections between the plurality of gate lines and the plurality of data lines. In order to apply a data voltage to each of the plurality of data lines, the data driver is required to include a number of output lines corresponding to the number of data lines. Since a plurality of integrated circuits are required, manufacturing costs of the display device increase. Disclosure of Invention One or more embodiments include a processor capable of preventing or reducing an increase in power consumption that may occur when the number of output lines is reduced, a display device including the processor, and an electronic device including the processor. However, aspects of the embodiments are not limited thereto, and the above characteristics do not limit the scope of the embodiments according to the present disclosure. Additional aspects will be set forth in part in the description which follows, and in part will be obvious from the description, or may be learned by practice of the presently disclosed embodiments. According to one or more embodiments, a display device includes a pixel unit including a plurality of pixels, each of the plurality of pixels being connected to a corresponding data line among a plurality of data lines, a corresponding gate line among a plurality of gate lines, and a corresponding light emission control line among a plurality of light emission control lines, a data driver outputting a data voltage through an output line, a data distribution circuit connecting each of the plurality of output lines to one of a corresponding pair of the plurality of data lines in response to a first control signal during a first subframe period, and connecting each of the plurality of output lines to the other of the corresponding pair of data lines in response to a second control signal during a second subframe period, the first gate driver sequentially outputting a first gate signal to each of the plurality of first gate lines among the plurality of gate lines during the first subframe period, the second gate driver sequentially outputting a second gate signal to each of the plurality of second gate lines among the plurality of gate lines during the second subframe period, and dividing the light emission control lines into groups of light emission control signals. In an embodiment, the data distribution circuit may connect each of the plurality of output lines to an odd-numbered data line of the corresponding pair of data lines during the first sub-frame period, and connect each of the plurality of output lines to an even-numbered data line of the corresponding pair of data lines during the second sub-frame period. In an embodiment, a plurality of pixels connected to odd-numbered data lines among the plurality of pixels may be connected to the plurality of first gate lines, respectively, and a plurality of pixels connected to even-numbered data lines among the plurality of pixels may be connected to the plurality of second gate lines, respectively. In an embodiment, the data distribution circuit may connect each of the odd-numbered output lines among the plurality of output lines to the odd-numbered data line among the corresponding pair of data lines and each of the even-numbered output lines among the plurality of output lines to the even-numbered data line among the corresponding pair of data lines during the first sub-frame period, and the data distribution circuit may connect each of the odd-numbered output lines among the plurality of output lines to the even-numbered data line among the corresponding pair of data lines and each of the even-numbered output lines among the plurality of output lines to the odd-numbered data line among the corresponding pair of data lines during the second sub-frame period. In an embodiment, the pixel unit may include first and second pixels connected to odd-numbered data lines among the corresponding pair of data lines and alternately arranged in a column direction, respectively, and third pixels connected to even-numbered data lines among the corresponding pair of data lines and repeatedly arranged in the column direction, and the first, second, and third pixels may emit different colors of light, respectively. In an embodiment, the data driver may alternately output the first color data voltage and the second color data voltage to each of the plurality of output lines in synchronization with an out