CN-121999725-A - Data driver and display device having the same

Abstract

A data driver and a display device having the same are disclosed. The display device includes a display panel configured to display an image and including pixels and data lines connected to the pixels, a timing controller configured to provide image data corresponding to the image, and a data driver including at least one output buffer configured to output analog data voltages corresponding to the image data to channels electrically connected to the data lines. The output buffer includes one or more transistors for applying a preset up current or down current to an output node connected to the channel to output a data voltage, and a capacitance adjusting circuit configured to adjust a capacitance of the output node based on an amplitude or a rate of a change in the data voltage between adjacent pixel rows.

Inventors

• Quan Enchen
• JIN XIANZHE
• PU SHILONG
• YU ZAIMIN

Assignees

• 乐金显示有限公司

Dates

Publication Date

20260508

Application Date

20250922

Priority Date

20241108

Claims (16)

1. 1. A display device, the display device comprising: A display panel configured to display an image, and including pixels and data lines connected to the pixels; A timing controller configured to provide image data corresponding to the image, and A data driver including at least one output buffer configured to output an analog data voltage corresponding to the image data to a channel electrically connected to a corresponding one of the data lines, Wherein the output buffer includes: One or more transistors configured to apply a preset up current or down current to an output node connected to the channel to output the data voltage, and A capacitance adjustment circuit configured to adjust the capacitance of the output node based on the magnitude or rate of change of the data voltage between adjacent pixel rows.
2. 2. The display device of claim 1, wherein the one or more transistors comprise: A pull-up transistor connected between a high voltage source or a high voltage node and the output node, and A pull-down transistor connected between the output node and a low voltage source or node.
3. 3. The display device according to claim 2, wherein the capacitance adjustment circuit includes: A compensation capacitor connected in parallel between the common node of the gates of the pull-up and pull-down transistors and the output node, and And switches, each of which is connected between the common node and a corresponding one of the ends of the compensation capacitor, and configured to be selectively switched based on output control information.
4. 4. A display device according to claim 3, wherein the switch is configured to control the number of compensation capacitors connected to the common node based on a voltage difference between a first data voltage supplied to a pixel of a previous pixel row and a second data voltage supplied to a current pixel row.
5. 5. The display device according to claim 4, wherein the number of compensation capacitors connected to the common node among the compensation capacitors decreases as a difference between the first data voltage and the second data voltage increases.
6. 6. The display device according to claim 4, wherein an equivalent capacitance of the compensation capacitor decreases as a difference between the first data voltage and the second data voltage increases.
7. 7. A display device according to claim 3, wherein the data driver further comprises: a latch circuit configured to reset the image data in parallel; A line memory configured to store the reset image data output from the latch circuit on a pixel-line basis; A comparison circuit configured to calculate a difference between the image data of the previous pixel row output from the row memory and the image data of the current pixel row output from the latch circuit, and And a controller configured to control on or off of the switch based on a calculation result of the comparison circuit.
8. 8. The display device according to claim 7, wherein the comparison circuit is configured to calculate a difference in the image data between the adjacent pixel rows for the channel.
9. 9. The display device according to claim 7, wherein the switch includes a first switch, a second switch, and a third switch, and Wherein the first switch, the second switch, and the third switch are turned on when the difference of the image data is less than a first threshold; When the difference of the image data is greater than or equal to the first threshold and less than a second threshold greater than the first threshold, two of the first switch, the second switch, and the third switch are turned on, and When the difference of the image data is greater than or equal to the second threshold, one of the first switch, the second switch, and the third switch is turned on.
10. 10. The display device of claim 7, wherein the data driver further comprises a digital-to-analog converter configured to convert the reset image data into the data voltage and provide the data voltage to the output buffer.
11. 11. A data driver, the data driver comprising: a latch circuit configured to reset image data supplied in series in parallel; A digital-to-analog converter configured to convert the reset image data into a data voltage, and An output buffer configured to output the data voltage to an output node connected to a data line, Wherein the output buffer includes: A capacitance adjustment circuit configured to adjust the capacitance of the output node based on the magnitude or rate of change between the continuously output data voltages.
12. 12. The data driver of claim 11, wherein the output buffer comprises one or more transistors configured to apply a preset up current or down current to the output node to output the data voltage.
13. 13. The data driver of claim 12, wherein the capacitance adjustment circuit comprises: A compensation capacitor connected in parallel between a common node of a gate of a pull-up transistor included in the one or more transistors and a gate of a pull-down transistor included in the one or more transistors and the output node, and And switches, each of which is connected between the common node and a corresponding one of the ends of the compensation capacitor, and configured to be selectively switched based on output control information.
14. 14. The data driver of claim 13, the data driver further comprising: a line memory configured to store reset image data output from the latch circuit based on one horizontal period; A comparison circuit configured to calculate a difference between the image data of the previous pixel row output from the row memory and the image data of the current pixel row output from the latch circuit, and And a controller configured to control on or off of the switch based on a calculation result of the comparison circuit.
15. 15. The data driver of claim 13, wherein the switch is configured to control the number of compensation capacitors connected to the common node based on a voltage difference between a first data voltage supplied to a pixel of a previous pixel row and a second data voltage supplied to a current pixel row.
16. 16. The data driver of claim 15, wherein an equivalent capacitance of the compensation capacitor decreases as a difference between the first data voltage and the second data voltage increases.

Description

Data driver and display device having the same Technical Field The present disclosure relates to an apparatus, particularly, for example, but not limited to, a display apparatus, and more particularly, to a data driver and a display apparatus including the same. Background In the information society of today, display devices for presenting images or visual information to users are increasingly important. The demand for such display devices has led to rapid development of display technology, and various types of display devices, such as Liquid Crystal Display (LCD) devices, organic Light Emitting Diode (OLED) display devices, and the like, have been developed and used. The display device may include a data driver configured to generate an analog driving signal required to drive the display panel, and the data driver may include an output amplifier, a buffer, and the like for outputting the analog driving signal. The description provided in the discussion of the background section should not be considered prior art merely because of the mention in or association with this section. The discussion of the background section may include information describing one or more aspects of the subject technology, and the description in this section is not intended to limit the present disclosure. Disclosure of Invention The inventors of the present disclosure have appreciated that the output amplifier or buffer may include at least one compensation capacitor to obtain a phase margin. The larger the capacity of the compensation capacitor, the larger the phase margin may be, and the more stable the output of the amplifier may be. In contrast, when the capacity of the compensation capacitor is large, the charge and discharge characteristics may be deteriorated, which may be disadvantageous for high-speed driving. One or more aspects of the present disclosure may provide a data driver configured to adjust a capacitance of an output node of an output buffer based on an amplitude (or rate) of a data voltage change. One or more aspects of the present disclosure may provide a display apparatus including a data driver. Aspects, examples, and embodiments provided in the present disclosure are not limited to the foregoing description, and various changes and modifications may be made without departing from the technical spirit and scope of the present disclosure. According to one or more example embodiments of the present disclosure, a display apparatus may be provided, the display apparatus including a display panel configured to display an image and including pixels and data lines connected to the pixels, a timing controller configured to provide image data corresponding to the image, and a data driver including at least one output buffer configured to output an analog data voltage corresponding to the image data to a channel electrically connected to the data lines. In one or more aspects, the output buffer may include one or more transistors for applying a preset up current or down current to an output node connected to the channel to output the data voltage, and a capacitance adjusting circuit configured to adjust a capacitance of the output node based on an amplitude or a rate of a change in the data voltage between adjacent pixel rows. In one or more aspects, the one or more transistors may include a pull-up transistor connected between the high voltage source or high voltage node and the output node and a pull-down transistor connected between the output node and the low voltage source or low voltage node. In one or more embodiments, the capacitance adjustment circuit may include a compensation capacitor connected in parallel between a common node of the gates of the pull-up and pull-down transistors and an output node, and a switch connected between the common node and a respective end of the compensation capacitor and selectively switching the compensation capacitor based on output control information. In one or more aspects, the switch may control the number of compensation capacitors connected to the common node based on a voltage difference between a first data voltage supplied to a pixel of a previous pixel row and a second data voltage supplied to a current pixel row. In one or more aspects, the number of compensation capacitors connected to the common node among the compensation capacitors may decrease as a difference between the first data voltage and the second data voltage increases. In one or more aspects, the equivalent capacitance of the compensation capacitor may decrease as the difference between the first data voltage and the second data voltage increases. In one or more embodiments, the data driver may further include a latch circuit configured to reset the image data in a parallel manner, a line memory configured to store the reset image data output from the latch circuit on a pixel line basis, a comparison circuit configured to calculate a difference between the image data of a previous pixel line output