CN-121999730-A - Display substrate and display device

Abstract

A display substrate and a display device. The display substrate comprises a substrate and a gate driving circuit arranged in a peripheral area of the substrate, wherein the gate driving circuit comprises a plurality of shift register units arranged in a first direction, each shift register unit comprises an input circuit, a control circuit, an output circuit and an output noise reduction circuit, the input circuit is connected with an input end and is configured to control the level of a first node in response to an input signal input by the input end, the control circuit is connected with a first node, a second node and a third node, the output circuit is connected with the third node and the output end respectively, the output noise reduction circuit is connected with the second node and the output end respectively, the control circuit comprises a first transistor and a first capacitor, the first electrode of the first transistor is connected with the second node and is configured to control the level of the second node, and the first transistor is located on one side, away from a first clock signal line, of the substrate.

Inventors

• SHANG GUANGLIANG
• LIU LIBIN
• WANG LI
• FENG YU
• WU BAOYUN

Assignees

• 京东方科技集团股份有限公司

Dates

Publication Date

20260508

Application Date

20220224

Priority Date

20210531

Claims (18)

1. 1. A display substrate, comprising: A substrate base plate, and A gate driving circuit disposed at a peripheral region of the substrate, wherein the gate driving circuit includes a plurality of shift register units arranged in a first direction, wherein, Each shift register unit comprises an input circuit, a control circuit, an output circuit and an output noise reduction circuit, The input circuit is connected to the input terminal and configured to control the level of the first node in response to an input signal input by the input terminal, The control circuit is connected with the first node, the second node and the third node, The output circuit is connected to the third node and the output terminal, respectively, and is configured to provide an output signal to the output terminal, The output noise reduction circuit is respectively connected with the second node and the output end and is configured to reduce noise of the output end, The control circuit comprises a first transistor and a first capacitor, wherein a first pole of the first transistor is connected with the second node and is configured to control the level of the second node, and the first transistor is located on one side, away from a first clock signal line, of the first capacitor on the substrate.
2. 2. The display substrate according to claim 1, wherein the control circuit further comprises a second transistor and a third transistor; A first pole of the second transistor is connected to the third node, a second pole of the second transistor is connected to a first power line to receive a first voltage, a gate of the second transistor is connected to the first node, the second transistor is configured to control a level of the third node in response to a level of the first node, A first pole of the third transistor is connected to the third node and configured to control a level of the third node.
3. 3. The display substrate of claim 2, wherein the control circuit further comprises a fifth transistor, wherein: A first pole of the fifth transistor is connected with the first power line to receive the first voltage, a second pole of the fifth transistor is connected with the second node, a gate of the fifth transistor is connected with a reset signal line, and the fifth transistor is configured to reset the second node; wherein, in the first direction, the active layer of the fifth transistor is located between the active layer of the first transistor and the active layer of the third transistor.
4. 4. The display substrate according to claim 3, wherein the control circuit further comprises a fourth transistor, wherein: the first pole of the fourth transistor is connected with the first power line to receive the first voltage, and the active layer of the fourth transistor and the active layer of the second transistor are integrally arranged.
5. 5. The display substrate according to claim 3, wherein the control circuit further comprises a seventh transistor, the input circuit comprises an eighth transistor, wherein, The first pole of the seventh transistor being connected to the second power supply line for receiving the second voltage, the second pole of the seventh transistor being connected to the fourth node, The active layers of the seventh transistor and the eighth transistor are sequentially arranged in the first direction and extend along the first direction.
6. 6. The display substrate of claim 5, wherein the control circuit further comprises a sixth transistor; A gate of the sixth transistor is connected to the first node, a first pole of the sixth transistor is connected to the first clock signal line to receive a first clock signal, and a second pole of the sixth transistor is connected to a fourth node; The active layer of the sixth transistor is located at a side of the active layer of the eighth transistor remote from the first clock signal line, and two channel regions of the sixth transistor extend in the first direction.
7. 7. The display substrate according to claim 5 or 6, wherein the control circuit further comprises a ninth transistor and a tenth transistor, wherein, A gate of the ninth transistor is connected to the second power line, a first pole of the ninth transistor is connected to the first node, and a second pole of the ninth transistor is connected to a second control node; The grid electrode of the tenth transistor is connected with the second control node, the first electrode of the tenth transistor is connected with the third clock signal line to receive a third clock signal, and the second electrode of the tenth transistor is connected with the first electrode of the first capacitor; a second pole of the first capacitor is connected with the second control node; The second control node is connected with the grid electrode of the first transistor, the grid electrode of the first transistor is connected with the second electrode of the first transistor, Wherein an active layer of the ninth transistor extends in the first direction.
8. 8. The display substrate according to claim 7, wherein the ninth transistor is arranged in order from the eighth transistor in the first direction.
9. 9. The display substrate according to claim 7, wherein the ninth transistor and the eighth transistor are closer to the first clock signal line than other transistors.
10. 10. A display substrate, comprising: A substrate base plate, and A gate driving circuit disposed at a peripheral region of the substrate, wherein the gate driving circuit includes a plurality of shift register units arranged in a first direction, wherein, Each shift register unit comprises an input circuit, a control circuit, an output circuit and an output noise reduction circuit, The input circuit is connected to the input terminal and configured to control the level of the first node in response to an input signal input by the input terminal, The control circuit is connected with the first node, the second node and the third node, The output circuit is connected to the third node and the output terminal, respectively, and is configured to provide an output signal to the output terminal, The output noise reduction circuit is respectively connected with the second node and the output end and is configured to reduce noise of the output end, Wherein the control circuit includes a first transistor, a ninth transistor, an eleventh transistor, and a first capacitor; a first pole of the first transistor is connected with the second node and is configured to control the level of the second node; A first pole of the ninth transistor is connected with the first node, and a second pole of the ninth transistor is connected with a second control node; A gate of the eleventh transistor is connected to the second power line, a first pole of the eleventh transistor is connected to a fourth node, and a second pole of the eleventh transistor is connected to a third control node; a second pole of the first capacitor is connected with the second control node; the second control node is connected with the grid electrode of the first transistor, and the grid electrode of the first transistor is connected with the second pole of the first transistor; The first capacitor includes an extension portion near the first clock signal line, and in the first direction, an orthographic projection of the extension portion on the substrate is located on one side of an orthographic projection of the eleventh transistor on the substrate and an orthographic projection of the ninth transistor on the substrate.
11. 11. The display substrate of claim 10, wherein the first transistor is located on a side of the first capacitor on the substrate away from the first clock signal line.
12. 12. The display substrate according to claim 10 or 11, wherein the control circuit further comprises a tenth transistor, wherein, A gate of the tenth transistor is connected to the second control node, a first pole of the tenth transistor is connected to a third clock signal line to receive a third clock signal, a second pole of the tenth transistor is connected to a first pole of the first capacitor, The tenth transistor is connected with the first pole of the first capacitor through a first via hole, and the orthographic projection of the first via hole on the substrate is positioned in the orthographic projection of the first capacitor on the substrate.
13. 13. The display substrate according to claim 10, wherein an active layer of the eleventh transistor extends in the first direction, and wherein an active layer of the ninth transistor and an active layer of the eleventh transistor are sequentially arranged in a second direction.
14. 14. The display substrate according to claim 13, wherein the control circuit further comprises a sixth transistor and a twelfth transistor; A gate of the sixth transistor is connected to the first node, a first pole of the sixth transistor is connected to the first clock signal line to receive a first clock signal, and a second pole of the sixth transistor is connected to the fourth node; A gate of the twelfth transistor is connected to the third control node, and a first pole of the twelfth transistor and a fourth clock signal line are connected to receive a fourth clock signal; and the orthographic projection of the active layer of the twelfth transistor on the substrate and the orthographic projection of the active layer of the sixth transistor on the substrate are positioned at one side of the orthographic projection of the first capacitor on the substrate.
15. 15. The display substrate of claim 10, wherein the active layer of the first transistor is connected to the first pole of the first transistor by a third via, an orthographic projection of a channel of the first transistor on the substrate not overlapping an orthographic projection of the third via on the substrate.
16. 16. The display substrate of claim 10, wherein the control circuit further comprises a seventh transistor, the input circuit comprises an eighth transistor, wherein, The first pole of the seventh transistor being connected to the second power supply line for receiving the second voltage, the second pole of the seventh transistor being connected to the fourth node, Wherein the orthographic projection of the active layer of the eighth transistor on the substrate and the orthographic projection of the active layer of the seventh transistor on the substrate are positioned at a first side of the orthographic projection of the first capacitor on the substrate.
17. 17. The display substrate of claim 16, wherein a front projection of the active layer of the first transistor on the substrate is on a second side of the first capacitor on the substrate, the first side of the first capacitor on the substrate being a side of the first capacitor on the substrate that is closer to the first clock signal line, and the second side of the first capacitor on the substrate being a side of the first capacitor on the substrate that is farther from the first clock signal line.
18. 18. A display device comprising the display substrate according to any one of claims 1-17.

Description

Display substrate and display device Cross Reference to Related Applications The application is a divisional application of an application patent application with the application number 202280000279.6, of which the application date is 2022, 02 and 24. The application patent application number 202280000279.6 claims priority from PCT international application number PCT/CN2021/097512 filed on 31 th 5 th 2021, the disclosure of which is incorporated herein by reference in its entirety as part of the present application. Technical Field Embodiments of the present disclosure relate to a display substrate and a display device. Background In the field of display technology, for example, a pixel array of a liquid crystal display panel or an Organic LIGHT EMITTING Diode (OLED) display panel generally includes a plurality of rows of gate lines and a plurality of columns of data lines disposed to cross the gate lines. The driving of the gate lines may be achieved by a bonded integrated driving circuit. With the continuous improvement of the manufacturing process of amorphous silicon thin film transistors or oxide thin film transistors in recent years, a gate line driving circuit may be directly integrated On a thin film transistor Array substrate to form GOA (GATE DRIVER On Array) to drive gate lines. For example, GOAs including a plurality of cascaded shift register units may be used to provide a switching state voltage signal (scan signal) to a plurality of rows of gate lines of a pixel array, so as to control the plurality of rows of gate lines to be sequentially opened, for example, and simultaneously provide a data signal to pixel units of corresponding rows in the pixel array by a data line, so as to form gray voltages required for each gray level of a display image at each pixel unit, thereby displaying one frame of image. Disclosure of Invention At least one embodiment of the present disclosure provides a display substrate including a substrate, and a gate driving circuit disposed at a peripheral region of the substrate, the gate driving circuit including a plurality of shift register units arranged in a first direction, each shift register unit including an input circuit, a control circuit, an output circuit, and an output noise reduction circuit, the input circuit being connected to an input terminal and configured to control a level of a first node in response to an input signal input from the input terminal, the control circuit being connected to the first node, a second node, a third node, the output circuit being connected to the third node and the output terminal, respectively, and configured to provide an output signal to the output terminal, the output noise reduction circuit being connected to the second node and the output terminal, respectively, and configured to provide a noise reduction control circuit including a first transistor and a first capacitor, the first electrode of the first transistor being connected to the second node and configured to control a level of the second node, the first transistor being located on a side of the substrate remote from a first clock signal line. For example, in the display substrate provided in an embodiment of the present disclosure, the control circuit further includes a second transistor and a third transistor, a first electrode of the second transistor is connected to the third node, a second electrode of the second transistor is connected to the first power line to receive the first voltage, a gate of the second transistor is connected to the first node, the second transistor is configured to control a level of the third node in response to a level of the first node, and the first electrode of the third transistor is connected to the third node and configured to control a level of the third node. For example, in the display substrate provided in an embodiment of the present disclosure, the control circuit further includes a fifth transistor, a first pole of the fifth transistor is connected to the first power line to receive the first voltage, a second pole of the fifth transistor is connected to the second node, a gate of the fifth transistor is connected to the reset signal line, the fifth transistor is configured to reset the second node, and an active layer of the fifth transistor is located between an active layer of the first transistor and an active layer of the third transistor in the first direction. For example, in the display substrate provided in an embodiment of the present disclosure, the control circuit further includes a fourth transistor, a first electrode of the fourth transistor is connected to the first power line to receive the first voltage, and an active layer of the fourth transistor and an active layer of the second transistor are integrally disposed. For example, in the display substrate provided in an embodiment of the present disclosure, the control circuit further includes a seventh transistor, the input circuit includes an e