CN-121999733-A - Scan driving circuit and display panel

CN121999733ACN 121999733 ACN121999733 ACN 121999733ACN-121999733-A

Abstract

The application discloses a scanning driving circuit and a display panel. The scan driving circuit includes a plurality of gate driving circuits and at least one level modulating circuit. The input end of the level modulation circuit is connected with the output end of the corresponding grid driving circuit one to one, and the level modulation circuit is used for generating and outputting a second scanning signal based on the first scanning signal, and the pulse width of the second scanning signal is larger than that of the first scanning signal. When the pulse width of the second scanning signal is larger than that of the first scanning signal and the second scanning signal is applied to the display scene in the low refresh rate mode, the pixel charging time of the corresponding display array can be effectively improved, the problem of insufficient charging caused by over-narrow pulse width is relieved, and accordingly display uniformity and picture stability are improved.

Inventors

WANG YING
YE LIDAN

Assignees

惠科股份有限公司

Dates

Publication Date: 20260508
Application Date: 20260330

Claims (10)

1. A scan driving circuit, comprising: A plurality of gate driving circuits for generating and outputting a first scan signal; The input end of the level modulation circuit is connected with the output end of the corresponding grid driving circuit one to one, and the level modulation circuit is used for generating and outputting a second scanning signal based on the first scanning signal, and the pulse width of the second scanning signal is larger than that of the first scanning signal.
2. The scan drive circuit according to claim 1, wherein the level modulation circuit includes a monostable waveform modulation circuit for generating and outputting the second scan signal based on the first scan signal.
3. The scan driving circuit according to claim 2, wherein the monostable waveform modulation circuit comprises a D flip-flop, a first delay capacitor and a first delay resistor, wherein the D flip-flop comprises an input control gate unit and an RS flip-flop; The signal input end of the input control gate unit is connected with the corresponding output end of the gate driving circuit, the clock input end of the input control gate unit is connected with a frame start pulse signal line, the two output ends of the input control gate unit are respectively connected with the R signal input end and the S signal input end of the RS trigger, the homodromous output end of the RS trigger is used for outputting the second scanning signal, the complementary output end of the RS trigger is connected with the first end of the first delay resistor, and the second end of the first delay resistor is connected with the S signal input end of the RS trigger through the first delay capacitor.
4. The scan driving circuit as recited in claim 3, wherein said monostable waveform modulation circuit includes a first gate switch and a plurality of gate branches, said gate branches including said first delay capacitor and said first delay resistor arranged in series, a common terminal of said first gate switch being connected to a complementary output terminal of said RS flip-flop, each gate terminal of said first gate switch being connected to a first terminal of each gate branch, and a second terminal of each gate branch being connected to an S signal input terminal of said RS flip-flop.
5. The scan drive circuit of claim 1, wherein the level modulation circuit comprises an RC delay circuit for generating and outputting the second scan signal based on the first scan signal.
6. The scan driving circuit according to claim 5, wherein the RC delay circuit comprises a second gate switch and a first delay unit, the first delay unit comprises a second delay resistor and a second delay capacitor, a common terminal of the second gate switch is connected to an output terminal of the corresponding gate driving circuit, a first gate terminal of the second gate switch is used for outputting the first scan signal, a second terminal of the second gate switch is connected to a first terminal of the second delay resistor, a second terminal of the second delay resistor is connected to a first terminal of the second delay capacitor and is used for outputting the second scan signal, and a second terminal of the second delay capacitor is grounded.
7. The scan drive circuit of claim 6, wherein the RC delay circuit further comprises a third gate switch, a fourth gate switch, and a second delay unit comprising a first voltage follower, a third delay resistor, and a third delay capacitor; The common end of the third gating switch is connected with the second end of the second delay resistor, the first gating end of the third gating switch is used for outputting the second scanning signal, the second gating end of the third gating switch is connected with the common end of the fourth gating switch, the first gating end of the fourth gating switch is connected with the input end of the first voltage follower, the second gating end of the fourth gating switch is grounded, the output end of the first voltage follower is connected with the first end of the third delay resistor, and the second end of the third delay resistor is connected with the first end of the third delay capacitor and is used for outputting the second scanning signal.
8. The scan driving circuit according to claim 1, wherein the level modulation circuit includes a pulse width modulation circuit for generating and outputting the second scan signal based on the first scan signal according to the received frequency switching signal.
9. The scan driving circuit according to claim 8, wherein the pulse width modulation circuit comprises a pulse width modulation module and an isolation unit; The input end of the pulse width modulation module is connected with the output end of the corresponding gate driving circuit, the output end of the pulse width modulation module is connected with the input end of the isolation unit, the output end of the isolation unit is used for outputting the second scanning signal, the pulse width modulation module is used for determining the rising edge of the second scanning signal based on the rising edge of the first scanning signal and determining the falling edge of the second scanning signal based on the frequency switching signal.
10. A display panel comprising a drive circuit and a pixel array, the drive circuit being connected to the pixel array, the drive circuit comprising a scan drive circuit according to any one of claims 1 to 9.

Description

Scan driving circuit and display panel Technical Field The application belongs to the technical field of display equipment, and particularly relates to a scanning driving circuit and a display panel. Background At present, a liquid crystal panel is one of important components of a liquid crystal display device, the liquid crystal panel comprises pixel units in rows and columns, and when the liquid crystal panel works, a row driving circuit can take one row of pixel units as a unit to provide a grid driving signal for a pixel circuit corresponding to the pixel units, so that the row scanning of the liquid crystal panel is completed, and the function of displaying images of the liquid crystal panel is realized. Q-Sync & M-Sync is a vertical synchronization technology for mobile terminals in the high-pass and concurrent departments, and can generate a scanning signal applied to a panel with a low refresh rate by adjusting VBLANK (vertical/interframe gap) between display pictures based on a scanning signal originally applied to a high refresh rate, but in an actual reliability test, the charging time of the scanning signal with the high refresh rate is shorter, the probability of generating bad results is higher, and the problems such as screen flashing, screen pattern, screen blacking and the like are very easy to occur. Disclosure of Invention The application aims to provide a scanning driving circuit and a display panel, and aims to solve the problem of shorter charging time in the traditional vertical synchronization technology. The first aspect of the embodiment of the application provides a scanning driving circuit, which comprises a plurality of grid driving circuits and at least one level modulation circuit, wherein the grid driving circuits are used for generating and outputting first scanning signals, the input ends of the level modulation circuits are connected with the output ends of the corresponding grid driving circuits one by one, and the level modulation circuits are used for generating and outputting second scanning signals based on the first scanning signals, and the pulse width of the second scanning signals is larger than that of the first scanning signals. In one embodiment, the level modulation circuit includes a monostable waveform modulation circuit for generating and outputting the second scan signal based on the first scan signal. In one embodiment, the monostable waveform modulation circuit comprises a D trigger, a first delay capacitor and a first delay resistor, wherein the D trigger comprises an input control gate unit and an RS trigger, a signal input end of the input control gate unit is connected with an output end of a corresponding gate driving circuit, a clock input end of the input control gate unit is connected with a frame starting pulse signal line, two output ends of the input control gate unit are respectively connected with an R signal input end and an S signal input end of the RS trigger, a homodromous output end of the RS trigger is used for outputting the second scanning signal, a complementary output end of the RS trigger is connected with a first end of the first delay resistor, and a second end of the first delay resistor is connected with an S signal input end of the RS trigger through the first delay capacitor. In one embodiment, the monostable waveform modulation circuit includes a first gating switch and a plurality of gating branches, the gating branches include a first delay capacitor and a first delay resistor which are arranged in series, a common end of the first gating switch is connected with a complementary output end of the RS trigger, each gating end of the first gating switch is connected with a first end of each gating branch, and a second end of each gating branch is connected with an S signal input end of the RS trigger. In one embodiment, the level modulation circuit includes an RC delay circuit for generating and outputting the second scan signal based on the first scan signal. In one embodiment, the RC delay circuit includes a second gate switch and a first delay unit, where the first delay unit includes a second delay resistor and a second delay capacitor, a common end of the second gate switch is connected to an output end of the corresponding gate driving circuit, a first gate end of the second gate switch is used for outputting the first scan signal, a second end of the second gate switch is connected to a first end of the second delay resistor, a second end of the second delay resistor is connected to a first end of the second delay capacitor and is used for outputting the second scan signal, and a second end of the second delay capacitor is grounded. In one embodiment, the RC delay circuit further includes a third gate switch, a fourth gate switch, and a second delay unit, where the second delay unit includes a first voltage follower, a third delay resistor, and a third delay capacitor, a common end of the third gate switch is connecte