CN-121999736-A - Display device, display driving chip and display driving method thereof

Abstract

The invention discloses a display device, a display driving chip and a display driving method thereof. The display area of the display panel includes a high refresh rate display area and a low refresh rate display area. The display driving chip generates a gate clock signal. The gate driver generates a first scan signal for driving the high refresh rate display area and a second scan signal for driving the low refresh rate display area using the gate clock signal. Both the high refresh rate display area and the low refresh rate display area are refreshed during the full brush frame period. Only the high refresh rate display area is refreshed during the partial brush frame period. The gate clock signal has different periods of operation or different amplitudes in different portions of the full brush frame period (corresponding to different refresh rate display regions).

Inventors

• Jian Zuohua

Assignees

• 联咏科技股份有限公司

Dates

Publication Date

20260508

Application Date

20251107

Priority Date

20241107

Claims (19)

1. 1. A display driver chip, the display driver chip comprising: a controller configured to generate a gate clock signal to control a gate driver of a display panel, wherein a display region of the display panel includes a high refresh rate display region and a low refresh rate display region, both the high refresh rate display region and the low refresh rate display region being refreshed during a full brush frame period, and only the high refresh rate display region being refreshed during a partial brush frame period; Wherein the gate driver generates a plurality of first scan signals to drive a plurality of scan lines of the high refresh rate display area and a plurality of second scan signals to drive a plurality of scan lines of the low refresh rate display area using the gate clock signal, and The gate clock signal has a first period of operation in a first portion of the full brush frame period, the first portion of the full brush frame period corresponding to the high refresh rate display region, and a second period of operation greater than the first period of operation in a second portion of the full brush frame period, the second portion of the full brush frame period corresponding to the low refresh rate display region.
2. 2. The display driver chip of claim 1, wherein the gate clock signal has a third period of the same length as the first operating period in a first portion of the partial brush frame period, the first portion of the partial brush frame period corresponding to the high refresh rate display region, and the gate clock signal stops switching in a second portion of the partial brush frame period, the second portion of the partial brush frame period corresponding to the low refresh rate display region.
3. 3. The display driver chip of claim 2, wherein the display driver chip, The controller is configured to output a reset pulse and an additional reset pulse to the gate driver during the partial brush frame period, and The reset pulse occurs before the plurality of gate clock signals begin switching and the additional reset pulse occurs after the plurality of gate clock signals cease switching during the partial brush frame period.
4. 4. The display driver chip of claim 2, wherein M and N are at least 1 in one refresh cycle consisting of M full brush frame periods and N partial brush frame periods, an average of a plurality of operation periods of the gate clock signal corresponding to the low refresh rate display region in the M full brush frame periods being approximately or equal to an average of a plurality of operation periods of the gate clock signal corresponding to the high refresh rate display region in the M full brush frame periods and a plurality of operation periods of the gate clock signal corresponding to the high refresh rate display region in the N partial brush frame periods.
5. 5. A display driver chip, the display driver chip comprising: a controller configured to output a gate clock signal to control a gate driver of a display panel, wherein a display region of the display panel includes a high refresh rate display region and a low refresh rate display region, both of which are refreshed during a full brush frame period and only the high refresh rate display region is refreshed during a partial brush frame period; The gate driver generating a plurality of first scan signals to drive a plurality of scan lines of the high refresh rate display area and a plurality of second scan signals to drive a plurality of scan lines of the low refresh rate display area using the gate clock signal, and The gate clock signal has a first amplitude in a first portion of the full brush frame period, the first portion of the full brush frame period corresponding to the high refresh rate display region, and a second amplitude greater than the first amplitude in a second portion of the full brush frame period, the second portion of the full brush frame period corresponding to the low refresh rate display region.
6. 6. The display driver chip of claim 5, wherein the gate clock signal has a third amplitude that is the same as the first amplitude in a first portion of the partial brush frame period, the first portion of the partial brush frame period corresponding to the high refresh rate display region, and the gate clock signal is maintained at an inactive voltage level in a second portion of the partial brush frame period, the second portion of the partial brush frame period corresponding to the low refresh rate display region.
7. 7. The display driver chip of claim 5, wherein the gate clock signal switches between a low logic level and a high logic level, and During the full brush frame period, the low logic level of the gate clock signal corresponding to the low refresh rate display region is lower than the low logic level of the gate clock signal corresponding to the high refresh rate display region.
8. 8. The display driver chip of claim 5, wherein the gate clock signal switches between a low logic level and a high logic level, and During the full brush frame period, the high logic level of the gate clock signal corresponding to the low refresh rate display area is higher than the high logic level of the gate clock signal corresponding to the high refresh rate display area.
9. 9. A display device, characterized in that the display device comprises: a display panel, comprising: An effective display area including a high refresh rate display area and a low refresh rate display area, and A gate driver for generating a plurality of first scan signals for driving a plurality of scan lines of the high refresh rate display area and a plurality of second scan signals for driving a plurality of scan lines of the low refresh rate display area, and A display driving chip comprising: A controller configured to generate a gate clock signal to control the gate driver of the display panel, wherein both the high refresh rate display area and the low refresh rate display area are refreshed during a full brush frame period and only the high refresh rate display area is refreshed during a partial brush frame period; Wherein the gate driver generates the plurality of first scan signals and the plurality of second scan signals using the gate clock signal, and The gate clock signal has a first period of operation in a first portion of the full brush frame period, the first portion of the full brush frame period corresponding to the high refresh rate display region, and a second period of operation greater than the first period of operation in a second portion of the full brush frame period, the second portion of the full brush frame period corresponding to the low refresh rate display region.
10. 10. The display device of claim 9, wherein the gate clock signal has a third period of the same length as the first operating period in a first portion of the partial brush frame period, the first portion of the partial brush frame period corresponding to the high refresh rate display region, and the gate clock signal stops switching in a second portion of the partial brush frame period, the second portion of the partial brush frame period corresponding to the low refresh rate display region.
11. 11. The display device of claim 10, wherein the display device comprises a display device, The controller is configured to output a reset pulse and an additional reset pulse to the gate driver during the partial brush frame period, and The reset pulse occurs before the plurality of gate clock signals begin switching and the additional reset pulse occurs after the plurality of gate clock signals cease switching during the partial brush frame period.
12. 12. The display device of claim 10, wherein M and N are at least 1 in one refresh cycle consisting of M full brush frame periods and N partial brush frame periods, an average of a plurality of operating periods of the gate clock signal corresponding to the low refresh rate display region in the M full brush frame periods being approximately or equal to an average of a plurality of operating periods of the gate clock signal corresponding to the high refresh rate display region in the M full brush frame periods and a plurality of operating periods of the gate clock signal corresponding to the high refresh rate display region in the N partial brush frame periods.
13. 13. A display device, characterized in that the display device comprises: a display panel, comprising: An effective display area including a high refresh rate display area and a low refresh rate display area, and A gate driver for generating a plurality of first scan signals for driving a plurality of scan lines of the high refresh rate display area and a plurality of second scan signals for driving a plurality of scan lines of the low refresh rate display area, and A display driving chip comprising: A controller configured to output a gate clock signal to control the gate driver of the display panel, wherein both the high refresh rate display area and the low refresh rate display area are refreshed during a full brush frame period and only the high refresh rate display area is refreshed during a partial brush frame period; Wherein the gate driver generates the plurality of first scan signals and the plurality of second scan signals using the gate clock signal, and The gate clock signal has a first amplitude in a first portion of the full brush frame period, the first portion of the full brush frame period corresponding to the high refresh rate display region, and a second amplitude greater than the first amplitude in a second portion of the full brush frame period, the second portion of the full brush frame period corresponding to the low refresh rate display region.
14. 14. The display device of claim 13, wherein the gate clock signal has a third amplitude that is the same as the first amplitude in a first portion of the local brush frame period, the first portion of the local brush frame period corresponding to the high refresh rate display region, and the gate clock signal is maintained at a non-active voltage level in a second portion of the local brush frame period, the second portion of the local brush frame period corresponding to the low refresh rate display region.
15. 15. The display device of claim 13, wherein the gate clock signal switches between a low logic level and a high logic level, and During the full brush frame period, the low logic level of the gate clock signal corresponding to the low refresh rate display region is lower than the low logic level of the gate clock signal corresponding to the high refresh rate display region.
16. 16. The display device of claim 13, wherein the gate clock signal switches between a low logic level and a high logic level, and During the full brush frame period, the high logic level of the gate clock signal corresponding to the low refresh rate display area is higher than the high logic level of the gate clock signal corresponding to the high refresh rate display area.
17. 17. A display driving method, characterized in that the display driving method comprises: A gate driver generating a gate clock signal to control a display panel, wherein a display region of the display panel includes a high refresh rate display region and a low refresh rate display region, both the high refresh rate display region and the low refresh rate display region being refreshed during a full brush frame period and only the high refresh rate display region being refreshed during a partial brush frame period; Wherein the gate driver generates a plurality of first scan signals to drive a plurality of scan lines of the high refresh rate display area using the gate clock signal and generates a plurality of second scan signals to drive a plurality of scan lines of the low refresh rate display area, and Wherein the gate clock signal has different periods of operation in respective periods of the full brush frame period or the gate clock signal has different amplitudes in respective periods of the full brush frame period.
18. 18. The display driving method according to claim 17, wherein the gate clock signal has a first operation period in a first portion of the full brush frame period, the first portion of the full brush frame period corresponding to the high refresh rate display area, the gate clock signal has a second operation period greater than the first operation period in a second portion of the full brush frame period, the second portion of the full brush frame period corresponding to the low refresh rate display area.
19. 19. The display driving method according to claim 17, wherein the gate clock signal has a first amplitude in a first portion of the full brush frame period, the first portion of the full brush frame period corresponding to the high refresh rate display region, the gate clock signal has a second amplitude greater than the first amplitude in a second portion of the full brush frame period, the second portion of the full brush frame period corresponding to the low refresh rate display region.

Description

Display device, display driving chip and display driving method thereof Technical Field The present invention relates to electronic circuits, and more particularly, to a display device, a display driving chip and a display driving method thereof. Background On a conventional display panel, all display areas of the display panel display one or more images at some same refresh rate (REFRESH RATE). In some applications, such as in a cell phone application, the entire display area of the display panel may be divided into multiple partitions, however, the different partitions all display images at the same refresh rate. In many use cases, only one partition often needs to frequently refresh the picture (e.g., play an animation), while another partition is a still picture and does not need to frequently refresh the picture. When all display regions (all partitions) of a conventional display panel are operated at a high refresh rate, the display panel consumes higher power. At this time, a high refresh rate is wasteful of power for partitions that do not need frequent refreshing of the picture. When the entire display area (all partitions) of the conventional display panel is operated at a low refresh rate, the display panel power consumption is low, but the refresh rate is too low for the partitions that need frequent refreshing of the picture. Disclosure of Invention The invention provides a display device, a display driving chip and a display driving method thereof, so that different display areas (partitions) in the same display panel adaptively have different frame rates (refresh rates). In an embodiment according to the present invention, the display driving chip described above includes a controller. The controller is configured to generate a gate clock signal to control a gate driver of the display panel, wherein a display area of the display panel includes a high refresh rate display area (HIGH REFRESH RATE DISPLAY AREA) and a low refresh rate display area (low REFRESH RATE DISPLAY AREA). Both the high refresh rate display area and the low refresh rate display area are refreshed during the full REFRESH FRAME period (full), while only the high refresh rate display area is refreshed during the partial PARTIAL REFRESH FRAME period. The gate driver generates a plurality of first scan signals and a plurality of second scan signals by using the gate clock signal, wherein the first scan signals are used for driving a plurality of scan lines of the high refresh rate display area, and the second scan signals are used for driving a plurality of scan lines of the low refresh rate display area. The gate clock signal has a first active period (active period) in a first portion of the full brush frame period (the first portion of the full brush frame period corresponds to the high refresh rate display region) and a second active period greater than the first active period in a second portion of the full brush frame period (the second portion of the full brush frame period corresponds to the low refresh rate display region). In an embodiment according to the present invention, the display driving chip described above includes a controller. The controller is configured to output a gate clock signal to control a gate driver of the display panel, wherein a display area of the display panel includes a high refresh rate display area and a low refresh rate display area. Both the high refresh rate display area and the low refresh rate display area are refreshed during the full brush frame period, while only the high refresh rate display area is refreshed during the partial brush frame period. The gate driver generates a plurality of first scan signals and a plurality of second scan signals using the gate clock signal, wherein the first scan signals are used for driving a plurality of scan lines of the high refresh rate display area, and the second scan signals are used for driving a plurality of scan lines of the low refresh rate display area. The gate clock signal has a first amplitude (swing) in a first portion of the full brush frame period (the first portion of the full brush frame period corresponds to the high refresh rate display region) and the gate clock signal has a second amplitude greater than the first amplitude in a second portion of the full brush frame period (the second portion of the full brush frame period corresponds to the low refresh rate display region). In an embodiment of the present invention, the display device includes a display panel and a display driving chip. The display panel includes an effective display area and a gate driver. The effective display area includes a high refresh rate display area and a low refresh rate display area. The gate driver is used for generating a plurality of first scanning signals for driving a plurality of scanning lines of the high refresh rate display area and a plurality of second scanning signals for driving a plurality of scanning lines of the low refresh rate d