CN-121999813-A - Storage system

Abstract

The present disclosure relates to storage systems. A storage system includes a substrate having a first substrate side and a second substrate side, and a storage medium including a first memory stack mounted over the substrate. The substrate includes a first signal substrate pad. The first signal substrate pad is closer to the first substrate side. The first memory stack includes a first memory chip and a second memory chip. The first memory chip includes a first outer chip pad and a first inner chip pad disposed adjacent to the first chip side. The second memory chip includes a second outer chip pad and a second inner chip pad disposed adjacent to the first chip side of the second memory chip. The respective first signal substrate pads, the respective first inner chip pads, and the respective second inner chip pads are electrically connected to each other.

Inventors

• LI XINGZHU

Assignees

• 爱思开海力士有限公司

Dates

Publication Date

20260508

Application Date

20250220

Priority Date

20241114

Claims (18)

1. 1. A storage system, comprising: a substrate having a first substrate side and a second substrate side opposite to the first substrate side, and A storage medium comprising a first memory stack mounted over the substrate, Wherein: the substrate includes a first signal substrate pad disposed over a surface of the substrate, wherein the first signal substrate pad is closer to the first substrate side than to the second substrate side, The first memory stack includes a first memory chip and a second memory chip offset stacked over the first memory chip, The first memory chip includes a first outer die pad and a first inner die pad, wherein the first outer die pad and first inner die pad are disposed adjacent to a first chip side of the first memory chip, wherein the first chip side of the first memory chip is closer to the first substrate side than to the second substrate side, The first outer die pad is disposed closer to the first chip side of the first memory chip than the first inner die pad, The second memory chip includes a second outer chip pad and a second inner chip pad, wherein the second outer chip pad and the second inner chip pad are disposed adjacent to a first chip side of the second memory chip, wherein the first chip side of the second memory chip is closer to the first substrate side than to the second substrate side, and The second outer chip pad is disposed closer to the first chip side of the second memory chip than the second inner chip pad, and The respective first signal substrate pads, the respective first inner chip pads, and the respective second inner chip pads are electrically connected to each other.
2. 2. The memory system of claim 1, wherein the first and second outer die pads are floating.
3. 3. The storage system of claim 1, Wherein the first memory stack comprises: a third memory chip offset stacked over the second memory chip, and A fourth memory chip offset stacked on the third memory chip, an Wherein the third memory chip includes a third outer chip pad and a third inner chip pad, wherein the third outer chip pad and the third inner chip pad are disposed adjacent to a first chip side of the third memory chip, the first chip side of the third memory chip being closer to the first substrate side than to the second substrate side, Wherein the third outer die pad is disposed closer to the first die side of the third memory chip than the third inner die pad, Wherein the fourth memory chip includes a fourth outer chip pad and a fourth inner chip pad, wherein the fourth outer chip pad and the fourth inner chip pad are disposed adjacent to a first chip side of the fourth memory chip, the first chip side of the fourth memory chip is adjacent to the first substrate side, Wherein the fourth outer die pad is disposed closer to the first die side of the fourth memory chip than the fourth inner die pad, Wherein the respective signal substrate pads, the respective first inner chip pads, the respective second inner chip pads, the respective third inner chip pads, and the respective fourth inner chip pads are electrically connected.
4. 4. The memory system of claim 3, wherein the third and fourth outer die pads are floating.
5. 5. A storage system according to claim 3, Wherein the substrate further comprises first to fourth power supply substrate pads provided on a surface of the substrate adjacent to the second substrate side, Wherein the first memory chip further comprises a first power chip pad disposed adjacent to a second chip side of the first memory chip, the second chip side of the first memory chip being opposite the first chip side of the first memory chip, Wherein the second memory chip further comprises a second power chip pad disposed adjacent to a second chip side of the second memory chip, the second chip side of the second memory chip being opposite the first chip side of the second memory chip, Wherein the third memory chip further comprises a third power chip pad disposed adjacent to a second chip side of the third memory chip, the second chip side of the third memory chip being opposite the first chip side of the third memory chip, Wherein the fourth memory chip further comprises a fourth power chip pad disposed adjacent to a second chip side of the fourth memory chip, the second chip side of the fourth memory chip being opposite the first chip side of the fourth memory chip, Wherein the first power supply substrate pad is electrically connected to the first power supply chip pad, Wherein the second power supply substrate pad is electrically connected to the second power supply chip pad, Wherein the third power supply substrate pad is electrically connected to the third power supply chip pad, and Wherein the fourth power supply substrate pad is electrically connected to the fourth power supply chip pad.
6. 6. The storage system of claim 1, further comprising: A memory controller; An interface circuit; a first parallel data channel between said memory controller and said interface circuit, and A second parallel data path between the interface circuit and the storage medium.
7. 7. The storage system of claim 6, Wherein the first parallel data channel comprises a DFI channel, DIF refers to DDR PHY interface, and Wherein the second parallel data channel comprises a GIO channel, GIO referring to global input/output.
8. 8. The storage system of claim 6, Wherein the storage medium further comprises a second memory stack mounted over the substrate, Wherein the substrate includes a second signal substrate pad exposed on a surface of the substrate adjacent to the first substrate side, and Wherein the second signal substrate pad is electrically connected to the second memory stack.
9. 9. The storage system of claim 8, Wherein the substrate further comprises a first signal substrate interconnect and a second signal substrate interconnect, Wherein the first signal substrate interconnect is electrically connected to a corresponding one of the first signal substrate pads, Wherein the second signal substrate interconnections are electrically connected to the respective second signal substrate pads, Wherein the second parallel data lanes comprise a first set of second parallel data lanes and a second set of second parallel data lanes, Wherein the first signal substrate interconnect is electrically connected to the first set of second parallel data channels, an Wherein the second signal substrate interconnect is electrically connected to the second set of second parallel data lanes.
10. 10. The memory system of claim 9, wherein the number of first parallel data channels is equal to a sum of the number of second parallel data channels in the first set of second parallel data channels and the number of second parallel data channels in the second set of second parallel data channels.
11. 11. A storage system, comprising: A memory controller; An interface circuit; a DFI lane located between the memory controller and the interface circuit, DFI referring to a DDR PHY interface; storage medium, and GIO channels, which are located between the interface circuit and the storage medium, GIO refers to global input/output, Wherein the storage medium includes a first memory stack and a second memory stack mounted over a substrate, Wherein each of the first and second memory stacks includes first and second memory chips offset stacked over the substrate, Wherein the substrate comprises: A first signal substrate interconnect and a second signal substrate interconnect electrically connected to the GIO channels, respectively; a first signal substrate pad electrically connected to the first signal substrate interconnect, and A second signal substrate pad electrically connected to the second signal substrate interconnect, and Wherein each of the first and second memory chips includes: An outer die pad and an inner die pad disposed adjacent to a first die side of each of the first and second memory chips, wherein the outer die pad is closer to the first die side of each of the first and second memory chips than the inner die pad, Wherein the first signal substrate pad is electrically connected to the inner chip pad of the first memory chip and the inner chip pad of the second memory chip of the first memory stack, and Wherein the second signal substrate pad is electrically connected to the inner chip pad of the first memory chip and the inner chip pad of the second memory chip of the second memory stack.
12. 12. The memory system of claim 11, wherein each of the DFI channel and the GIO channel comprises a plurality of data channels coupled in parallel.
13. 13. The memory system of claim 11, wherein the number of DFI lanes and the number of GIO lanes are the same.
14. 14. The storage system of claim 13, Wherein the GIO pathway comprises: a first set of the GIO channels electrically connected to the first memory stack, an A second set of the GIO channels electrically connected to the second memory stack.
15. 15. The memory system of claim 11, wherein the outer die pads of the first and second memory chips are each floating.
16. 16. The storage system of claim 11, Wherein the substrate further comprises a power supply substrate pad, Wherein the first and second memory chips further comprise a power chip pad disposed adjacent to a second chip side of each of the first and second memory chips, wherein the second chip side is opposite to the first chip side, and Wherein the power supply substrate pad is electrically connected to the power supply chip pad.
17. 17. The storage system of claim 11, Wherein the first memory chip includes: a first lower memory chip; A first intermediate memory chip offset stacked above the first lower memory chip, and A first upper memory chip offset stacked above the first intermediate memory chip, Wherein the outer chip pad includes: a first lower outer die pad disposed adjacent to a first die side of the first lower memory die; a first intermediate outer chip pad disposed adjacent to a first chip side of the first intermediate memory chip, and A first upper outer die pad disposed adjacent to a first die side of the first upper memory die, Wherein the inner chip bonding pad comprises: A first lower inner die pad disposed adjacent to the first lower outer die pad, wherein the first lower outer die pad is closer to the first chip side of a first lower memory chip than the first lower inner die pad; A first intermediate inner chip pad disposed adjacent to the first intermediate outer chip pad, wherein the first intermediate outer chip pad is closer to the first chip side of the first intermediate memory chip than the first intermediate inner chip pad, and A first upper inner die pad disposed adjacent to the first upper outer die pad, wherein the first upper outer die pad is closer to the first chip side of the first upper memory chip than the first upper inner die pad, Wherein the respective first signal substrate pads, the respective first lower inner chip pads, the respective first intermediate inner chip pads, and the respective first upper inner chip pads are electrically connected.
18. 18. The storage system of claim 17, Wherein the second memory chip includes: a second lower memory chip; A second intermediate memory chip offset stacked above the second lower memory chip, and A second upper memory chip offset stacked above the second intermediate memory chip, Wherein the outer chip pad includes: a second lower outer die pad disposed adjacent to the first die side of the second lower memory die; a second intermediate outer chip pad disposed adjacent to the first chip side of the second intermediate memory chip, and A second upper outer die pad disposed adjacent to the first die side of the second upper memory die, Wherein the inner chip bonding pad comprises: A second lower inner die pad disposed adjacent to the second lower outer die pad, wherein the second lower outer die pad is closer to the first die side of the second lower memory die than the second lower inner die pad; A second intermediate inner die pad disposed adjacent to the second intermediate outer die pad, wherein the second intermediate outer die pad is closer to the first die side of the second intermediate memory die than the second intermediate inner die pad, and A second upper inner die pad disposed adjacent to the second upper outer die pad, wherein the second upper outer die pad is closer to the first die side of the second upper memory die than the second upper inner die pad, Wherein the respective second signal substrate pads, the respective second lower inner chip pads, the respective second intermediate inner chip pads, and the respective second upper inner chip pads are electrically connected.

Description

Storage system Cross Reference to Related Applications The present application claims priority from U.S. patent application Ser. No. 18/934,803, filed on 1 month 11 of 2024, and from Korean patent application Ser. No. 10-2024-0162080, filed on 14 month 11 of 2024, both of which are incorporated herein by reference in their entireties. Technical Field Embodiments of the present disclosure relate to a storage system including a controller and a memory stack. Background A variety of memory systems for high speed operation and low power consumption are under study. Disclosure of Invention Embodiments of the present disclosure provide a memory system that includes a controller and a memory stack. An embodiment of the present disclosure provides a memory system in which a controller and a memory chip directly communicate with each other through channels arranged in parallel without a SERDES (serializer/deserializer). An embodiment of the present disclosure provides a memory system having a memory stack in which all stacked memory chips operate in a slave mode. An embodiment of the present disclosure provides a method for operating a memory chip serving as a master chip in a slave mode. According to one embodiment of the present disclosure, a storage system includes a substrate having a first substrate side and a second substrate side opposite the first substrate side, and a storage medium including a first memory stack mounted over the substrate. The substrate includes a first signal substrate pad disposed over a surface of the substrate. The first signal substrate pad is closer to the first substrate side than to the second substrate side. The first memory stack includes a first memory chip and a second memory chip offset stacked over the first memory chip. The first memory chip includes a first outer chip pad and a first inner chip pad. The first outer chip pad and the first inner chip pad are disposed adjacent to a first chip side of the first memory chip. The first chip side of the first memory chip is closer to the first substrate side than to the second substrate side. The first outer die pad is disposed closer to the first chip side of the first memory chip than the first inner die pad. The second memory chip includes a second outer chip pad and a second inner chip pad. The second outer chip pad and the second inner chip pad are disposed adjacent to the first chip side of the second memory chip. The first chip side of the second memory chip is closer to the first substrate side than to the second substrate side. The second outer chip pad is disposed closer to the first chip side of the second memory chip than the second inner chip pad. The respective first signal substrate pads, the respective first inner chip pads, and the respective second inner chip pads are electrically connected to each other. According to another embodiment of the present disclosure, a memory system includes a memory controller, an interface circuit, a DDR PHY interface (DFI) channel between the memory controller and the interface circuit, a storage medium, and a global input/output (GIO) channel between the interface circuit and the storage medium. The storage medium includes a first memory stack and a second memory stack mounted over a substrate. Each of the first and second memory stacks includes first and second memory chips that are offset stacked over a substrate. The substrate includes a first signal substrate interconnect and a second signal substrate interconnect electrically connected to the global input/output channel, respectively, a first signal substrate pad electrically connected to the first signal substrate interconnect, and a second signal substrate pad electrically connected to the second signal substrate interconnect. Each of the first and second memory chips includes an outer chip pad and an inner chip pad disposed adjacent to a respective first chip side of the first and second memory chips. Drawings Fig. 1 is a block diagram schematically illustrating an electronic system according to an embodiment of the present disclosure. Fig. 2 is a block diagram schematically illustrating a computing quick link (Compute eXpress Link (CXL)) controller according to an embodiment of the disclosure. Fig. 3 is a block diagram schematically illustrating a storage medium according to an embodiment of the present disclosure. Fig. 4 is a block diagram schematically illustrating data channels for data communication in a storage system according to an embodiment of the present disclosure. Fig. 5A and 5B are top and side views schematically illustrating one memory stack according to an embodiment of the present disclosure. Fig. 6 is a circuit diagram schematically illustrating a memory system according to an embodiment of the present disclosure. Fig. 7 illustrates a memory chip operating in a slave mode according to an embodiment of the present disclosure. Detailed Description Embodiments of the present disclosure will be described in