CN-121999817-A - Multi-voltage supply system for OTP memory

CN121999817ACN 121999817 ACN121999817 ACN 121999817ACN-121999817-A

Abstract

The invention discloses a multi-voltage supply system for an OTP memory, which comprises a band gap reference unit, a first buffer, a second buffer, a protection voltage generation unit, a programming voltage generation unit, a reading and writing voltage generation unit and a logic unit, wherein the protection voltage generation unit is used for generating protection voltage through a charge pump, the programming voltage generation unit is used for generating programming voltage through the charge pump, and the reading and writing voltage generation unit is used for generating reading and writing voltage through voltage clamping. The invention effectively solves the defects of the traditional scheme in voltage precision, power consumption and flexibility, obviously reduces the ripple wave of the output voltage, ensures the high stability and temperature adaptability of the output voltage, and obviously improves the integration level, the power consumption optimization and the dynamic regulation capability.

Inventors

GUO YUCHEN
LIAO HONG
YAN GANG
ZHU LIN
CAO NING
WEI LIN
Zuo Jiangyu

Assignees

中国电子科技集团公司第二十四研究所

Dates

Publication Date: 20260508
Application Date: 20260127

Claims (10)

1. A multi-voltage supply system for OTP memory is characterized by comprising A bandgap reference unit for generating a temperature independent reference voltage SPIVDD' based on the analog voltage SPIVDD for the first buffer and the second buffer; The first buffer is used for enhancing the driving capability of the reference voltage and outputting a first driving voltage, and the first driving voltage is respectively sent to the protection voltage generating unit, the programming voltage generating unit and the read-write voltage generating unit; The second buffer is used for outputting a second driving voltage after enhancing the driving capability of the reference voltage and sending the second driving voltage to the read-write voltage generating unit; A protection voltage generation unit for generating a protection voltage VO0 by a charge pump; a programming voltage generation unit for generating a programming voltage VO1 by a charge pump; A read-write voltage generation unit for generating a read-write voltage VO2 by voltage clamping, and And the logic unit is used for generating each logic control signal.
2. The multi-voltage supply system for an OTP memory of claim 1 wherein said logic control signal comprises a clock signal S_CLK, an enable signal ENP and a multi-way digital signal ADJ.
3. The multi-voltage supply system for OTP memory of claim 2 wherein said protection voltage generating unit comprises The first resistance adjusting module is used for dividing the first driving voltage by taking three paths of digital signals ADJ as control signals thereof and outputting the divided first driving voltage; the non-inverting input end of the first comparator is electrically connected with the output end of the first resistance adjusting module, the inverting input end of the first comparator is electrically connected with the output end of the first voltage feedback module, and the two output ends of the first comparator are electrically connected with the upper charge pump circuit; An upper charge pump circuit for controlling the charge pump to generate a corresponding protection voltage VO0 according to the output signal of the first comparator and the clock signal S_CLK, and The first voltage feedback module is used for dividing the protection voltage and feeding the divided protection voltage back to the inverting input end of the first comparator.
4. The multi-voltage supply system for an OTP memory of claim 3 wherein said upper charge pump circuit comprises a first clock generation circuit and a plurality of upper charge pumps, said upper charge pumps are voltage multiplication type charge pumps, the signal input terminal of each of said upper charge pumps is connected with analog voltage SPIVDD, said first clock generation circuit is used for generating a plurality of first delay clocks according to clock signal S_CLK and two output voltage signals of a first comparator, said first delay clocks are in one-to-one correspondence with the upper charge pumps, and each of said first delay clocks is connected to the clock input terminal of the corresponding upper charge pump, respectively, and the output terminals of said plurality of upper charge pumps are connected in parallel and then used as the output terminals of the upper charge pump circuit.
5. The multi-voltage supply system for the OTP memory of claim 3 wherein the first comparator comprises a first PMOS tube MP1, a second PMOS tube MP2, a third PMOS tube MP3, a fourth PMOS tube MP4, a fifth PMOS tube MP5, a sixth PMOS tube MP6, a seventh PMOS tube MP7, a first NMOS tube MN1, a second NMOS tube MN2, a third NMOS tube MN3, a fourth NMOS tube MN4, a fifth NMOS tube MN5, a sixth NMOS tube MN6, a seventh NMOS tube MN7, an eighth NMOS tube MN8, and a capacitor C1; The grid electrodes of the seventh PMOS tube MP7, the first PMOS tube MP1, the fourth PMOS tube MP4, the fifth PMOS tube MP5 and the sixth PMOS tube MP6 are all connected with a reference voltage SPIVDD', the grid electrodes of the seventh PMOS tube MP7 are respectively and electrically connected with the drain electrodes of the seventh PMOS tube MP7, the grid electrodes of the first PMOS tube MP1, the grid electrodes of the fourth PMOS tube MP4 and the drain electrodes of the fifth NMOS tube MN5, the grid electrodes of the sixth NMOS tube MN6 and the grid electrodes of the seventh NMOS tube MN7 are all connected with an enable signal ENP, the source electrodes of the fifth NMOS tube MN5 are electrically connected with the drain electrodes of the sixth NMOS tube MN6, the source electrodes of the sixth NMOS tube MN6 are electrically connected with the drain electrodes of the seventh NMOS tube MN7, and the source electrodes of the seventh NMOS tube MN7 are connected with digital ground; The drain electrode of the first PMOS tube MP1 is respectively and electrically connected with the source electrode of the second PMOS tube MP2 and the source electrode of the third PMOS tube MP3, the grid electrode of the second PMOS tube MP2 is used as the inverting input end of the first comparator, the grid electrode of the third PMOS tube MP3 is used as the non-inverting input end of the first comparator, the drain electrode of the second PMOS tube MP2 is respectively and electrically connected with the drain electrode and the grid electrode of the eighth NMOS tube MN8, and the source electrode of the eighth NMOS tube MN8 is connected with the digital DGND; The drain electrode of the fourth PMOS transistor MP4 is electrically connected to the drain electrode of the second NMOS transistor MN2, the gate electrode of the third NMOS transistor MN3, and the first end of the capacitor C1, and the source electrode of the second NMOS transistor MN2 and the second end of the capacitor C1 are connected to the digital DGND; The grid electrode of the fifth PMOS tube MP5 is respectively and electrically connected with the drain electrode of the third NMOS tube MN3 and the grid electrode of the sixth PMOS tube MP6 to be used as a first output end of the first comparator for outputting the bias voltage PVBO, the drain electrode of the sixth PMOS tube MP6 is respectively and electrically connected with the drain electrode of the fourth NMOS tube MN4 and the grid electrode to be used as a second output end of the first comparator for outputting the bias voltage PVBO, and the source electrodes of the third NMOS tube MN3 and the fourth NMOS tube MN4 are both connected with the digital DGND.
6. The multi-voltage supply system for OTP memory of claim 4 wherein the first clock generation circuit comprises a first NAND gate U1, a second NAND gate U2, a third NAND gate U3, a fifth NAND gate U5, a first NAND gate N1, a plurality of second NAND gates, a fourth NAND gate N4 and a plurality of delay output units, wherein the delay output units and the second NAND gates are in one-to-one correspondence with the upper charge pump; The second input end of the first nand gate U1 is connected with a low-level signal CLKIN, the first input end of the first nand gate U1 and the second input end of the second nand gate U2 are both connected with a clock signal s_clk, the first input end and the second input end of the third nand gate U3 are respectively and electrically connected with the output end of the first nand gate U1 and the output end of the second nand gate U2, the plurality of second nand gates are sequentially connected in series between the output end of the third nand gate U3 and the first input end of the fifth nand gate U5, the first input end of the fifth nand gate U5 is electrically connected with the output end of the fourth nand gate N4, the second input end of the fifth nand gate U5 is connected with a high level, and the output end of the fifth nand gate U5 and the input end of the fourth nand gate N4 are both electrically connected with the first input end of the second nand gate U2.
7. The multi-voltage supply system for the OTP memory of claim 6 wherein the delay output unit comprises a third NOT gate and a fourth NOT gate, wherein the output end of the third NOT gate is electrically connected with the first input end of the fourth NOT gate to serve as the input end of the delay output unit, the input end of the third NOT gate is electrically connected with the output end of the fourth NOT gate to serve as the output end of the delay output unit to output the delay clock CLK_OUT, and the second input end of the fourth NOT gate is connected with a high level.
8. The multi-voltage supply system for OTP memory of claim 2 wherein said read-write voltage generating unit comprises The second resistance adjusting module is used for dividing the first driving voltage by taking the other three paths of the multipath digital signals ADJ as control signals thereof and outputting the divided first driving voltage; The non-inverting input end of the second comparator is electrically connected with the output end of the second resistance adjusting module, the inverting input end of the second comparator is electrically connected with the output end of the second voltage feedback module, and the two output ends of the second comparator are electrically connected with the lower charge pump circuit; A lower charge pump circuit for controlling the charge pump to generate corresponding read-write voltage VO1 according to the output signal of the second comparator and the clock signal S_CLK, and The second voltage feedback module is used for dividing the read-write voltage and feeding back the divided read-write voltage to the inverting input end of the second comparator.
9. The multi-voltage supply system for the OTP memory of claim 8 wherein the lower charge pump circuit comprises a second clock generation circuit and a plurality of lower charge pumps, the lower charge pumps are voltage multiplication type charge pumps, the second clock generation circuit is used for generating a plurality of second delay clocks according to a clock signal S_CLK and two output voltage signals of a second comparator, the second delay clocks are in one-to-one correspondence with the lower charge pumps, each second delay clock is respectively connected to a clock input end of the corresponding lower charge pump, signal input ends of the plurality of lower charge pumps are connected with a protection voltage VO0, and output ends of the plurality of lower charge pumps are connected in parallel and then serve as output ends of the upper charge pump circuit.
10. The multi-voltage supply system for an OTP memory according to any one of claims 1 to 9, wherein the read-write voltage generating unit comprises a first level shift module and a second level shift module, a first input end of the first level shift module is connected with a first driving voltage, a second input end of the first level shift module is connected with a second driving voltage, an output end of the second level shift module is electrically connected with a first input end of the second level shift module, a power end of the second level shift module is connected with a protection voltage VO0, a first output end of the second level shift module is used for outputting a read-write voltage VO2, a second output end of the second level shift module is electrically connected with a third input end of the first level shift module, the first level shift module is used for clamping the first driving voltage input by the first input end of the first level shift module through the second driving voltage input by the second input end of the first level shift module and then outputting the voltage fed back to the first level shift module as the read-write voltage VO2 through the second level shift module, and the read-write voltage 2 is fed back to the first level shift module through the second output end of the second level shift module is enabled to enhance the clamping effect.

Description

Multi-voltage supply system for OTP memory Technical Field The present invention relates to the field of semiconductor memory circuits, and more particularly to a multi-voltage supply system for an OTP memory. Background With the development of semiconductor technology, OTP (one-time programmable) memories are widely applied in the fields of Internet of things equipment, security authentication chips and the like due to simple structures and high reliability. The normal operation depends on three key voltages, namely a read voltage, a programming voltage and a protection voltage, and the design of a power supply system directly influences the performance of the memory. The current common power supply modes mainly comprise a built-in voltage generation scheme for generating required voltage through an internal circuit of a chip and a factory preset scheme for directly using fixed voltage provided by the outside. The built-in scheme has high integration level, but also has obvious short plates, namely, the voltage precision is limited due to insufficient matching among different voltage channels, the conversion efficiency of the boost circuit is low, the output voltage ripple is large, and the protection voltage is usually fixed and is difficult to dynamically adjust according to the working state. The external scheme is simple in design, but lacks flexibility, and cannot adapt to the dynamic requirements of different application scenes on voltage. The above problems are increasingly pronounced as process dimensions continue to shrink. On the one hand, the core working voltage is continuously reduced, but the high voltage required by programming is still required to be maintained, so that the design contradiction of the built-in voltage circuit is aggravated, and on the other hand, the influence of the process fluctuation on the voltage stability is more remarkable. While the prior art may alleviate the problem by adding calibration modules or optimizing local structures, the challenges of multi-voltage coordination supplies are not addressed at all at the system level, often at the expense of increased chip area or power consumption. Therefore, it is particularly urgent to design a new multi-voltage supply system. The ideal power supply scheme combines the dual advantages of internal integration and external stability, can intelligently generate and cooperatively control three working voltages, and keeps lower power consumption while realizing high-precision output and dynamic flexible regulation. Such a system would significantly improve the performance and applicability of OTP memory, providing solid and reliable storage support for more critical applications. Disclosure of Invention In order to overcome the defects of the prior art, the technical problem to be solved by the invention is to provide a multi-voltage supply system for an OTP memory. In order to solve the technical problems, the invention provides the following technical scheme: A multi-voltage supply system for OTP memory includes A bandgap reference unit for generating a temperature independent reference voltage SPIVDD' based on the analog voltage SPIVDD for the first buffer and the second buffer; The first buffer is used for enhancing the driving capability of the reference voltage and outputting a first driving voltage, and the first driving voltage is respectively sent to the protection voltage generating unit, the programming voltage generating unit and the read-write voltage generating unit; The second buffer is used for outputting a second driving voltage after enhancing the driving capability of the reference voltage and sending the second driving voltage to the read-write voltage generating unit; A protection voltage generation unit for generating a protection voltage VO0 by a charge pump; a programming voltage generation unit for generating a programming voltage VO1 by a charge pump; A read-write voltage generation unit for generating a read-write voltage VO2 by voltage clamping, and And the logic unit is used for generating each logic control signal. Further, the logic control signals include a clock signal s_clk, an enable signal ENP, and a multi-channel digital signal ADJ. Further, the protection voltage generation unit includes The first resistance adjusting module is used for dividing the first driving voltage by taking three paths of digital signals ADJ as control signals thereof and outputting the divided first driving voltage; the non-inverting input end of the first comparator is electrically connected with the output end of the first resistance adjusting module, the inverting input end of the first comparator is electrically connected with the output end of the first voltage feedback module, and the two output ends of the first comparator are electrically connected with the upper charge pump circuit; An upper charge pump circuit for controlling the charge pump to generate a corresponding protection voltage VO0 according to