CN-121999818-A - Low ripple charge pump circuit

CN121999818ACN 121999818 ACN121999818 ACN 121999818ACN-121999818-A

Abstract

The invention discloses a low-ripple charge pump circuit which comprises a non-overlapping clock circuit and a charge pump main body circuit, wherein the non-overlapping clock circuit is used for generating a first clock signal and a second clock signal which are non-overlapping according to an external clock signal, and the charge pump main body circuit is used for boosting an input voltage according to the first clock signal and the second clock signal to form a charge pump output voltage and a dynamic substrate bias voltage. In the invention, the non-overlapping clock signals are adopted to effectively reduce the reverse leakage current loss, avoid the reverse leakage current generated by the conduction of the paths between the input and the output due to the simultaneous conduction of the switching tubes of the charge pump, and meet the requirements of high stability and low loss of the OTP memory circuit.

Inventors

GUO YUCHEN
LIAO HONG
YAN GANG
ZHU LIN
CAO NING
ZHU YIXIAO
CHEN KEQUAN

Assignees

中国电子科技集团公司第二十四研究所

Dates

Publication Date: 20260508
Application Date: 20260127

Claims (10)

1. A low ripple charge pump circuit is characterized by comprising A non-overlapping clock circuit for generating a first clock signal CLK_1 and a second clock signal CLK_2 which are non-overlapping based on an external clock signal CLK, and The charge pump body circuit is used for boosting the input voltage VIN according to the first clock signal CLK_1 and the second clock signal CLK_2 to form a charge pump output voltage VOUT0 and a dynamic substrate bias voltage VOUT1.
2. The low ripple charge pump circuit of claim 1, wherein the non-overlapping clock circuit comprises an inverter INV1, a NAND gate NAND2, a buffer BUF1, a buffer BUF2, a first phase delay unit and a second phase delay unit, wherein the first phase delay unit and the second phase delay unit are used for carrying out phase delay on an input signal and outputting the input signal; The input end of the inverter INV1 and the second input end of the NAND gate NAND2 are electrically connected with the input end of the non-overlapping clock circuit and are used for accessing an external clock signal CLK; The first input end of the NAND gate NAND1 is electrically connected with the output end of the first phase delay unit, and the output end of the NAND gate NAND1 is electrically connected with the input end of the second phase delay unit and the input end of the buffer BUF1 respectively; The first input end of the NAND gate NAND2 is electrically connected with the output end of the second phase delay unit, the output end of the NAND gate NAND2 is electrically connected with the input end of the first phase delay unit and the input end of the buffer BUF2 respectively, and the output end of the buffer BUF2 is electrically connected with the second output end of the non-overlapping clock circuit and is used for outputting a second clock signal CLK_2.
3. The low-ripple charge pump circuit of claim 2, wherein the first phase delay unit comprises an inverter INV2, an inverter INV3, an inverter INV4 and a NAND gate NAND3, wherein an input end of the inverter INV2 and a first input end of the NAND gate NAND3 are electrically connected to be used as an input end of the first phase delay unit, an output end of the inverter INV2 is electrically connected to an input end of the inverter INV3, an output end of the inverter INV2 is electrically connected to a second input end of the NAND gate NAND3, an output end of the NAND gate NAND3 is electrically connected to an input end of the inverter INV4, and an output end of the inverter INV4 is used as an output end of the first phase delay unit.
4. The low-ripple charge pump circuit of claim 3, wherein the second phase delay unit comprises an inverter INV5, an inverter INV6, an inverter INV7 and a NAND gate NAND4, wherein an input end of the inverter INV5 is electrically connected with a first input end of the NAND gate NAND4 and then used as an input end of the second phase delay unit, an output end of the inverter INV5 is electrically connected with an input end of the inverter INV6, an output end of the inverter INV5 is electrically connected with a second input end of the NAND gate NAND4, an output end of the NAND gate NAND4 is electrically connected with an input end of the inverter INV7, and an output end of the inverter INV7 is used as an output end of the second phase delay unit.
5. The low-ripple charge pump circuit of any one of claims 1 to 4, wherein the charge pump body circuit comprises An inverting circuit for generating a corresponding inverted signal according to the first clock signal clk_1 and the second clock signal clk_2; the boost control circuit is used for generating a first boost control signal and a second boost control signal after boosting the input voltage VIN under the control of the first clock signal CLK_1 and the second clock signal CLK_2 respectively; The boost circuit is used for generating a first boost signal and a second boost signal after boosting the input voltage VIN under the control of the first boost control signal, the second boost control signal and the reverse signal output by the first control circuit respectively; An output control circuit for generating a first output control signal and a second output control signal based on the inverted signal output from the first control circuit, and And the output circuit is used for respectively outputting the output voltage VOUT0 of the charge pump and the bias voltage VOUT1 of the dynamic substrate bias after reducing the ripple of the first boost signal and the second boost signal under the control of the first output control signal and the second output control signal.
6. The low-ripple charge pump circuit of claim 5, wherein the inverting circuit comprises an inverter INV8, an inverter INV9, a PMOS transistor MP0, a PMOS transistor MP1, an NMOS transistor MN4, and an NMOS transistor MN5; The input end of the inverter INV8 and the grid electrode of the NMOS tube MN5 are electrically connected with the first clock input end of the charge pump main body circuit and are used for being connected with a first clock signal CLK_1, the output end of the inverter INV8 is respectively and electrically connected with the grid electrode of the PMOS tube MP0 and the output control circuit, the source electrode of the PMOS tube MP0 is connected with the analog voltage AVDD, the drain electrode of the PMOS tube MP0 is respectively and electrically connected with the drain electrode of the NMOS tube MN4 and the boost circuit, and the source electrode of the NMOS tube MN4 is grounded; The input end of the inverter INV9 and the grid electrode of the NMOS tube MN4 are electrically connected with the second clock input end of the charge pump main body circuit and are used for being connected with a second clock signal CLK_2, the output end of the inverter INV9 is respectively and electrically connected with the grid electrode of the PMOS tube MP1 and the output control circuit, the source electrode of the PMOS tube MP1 is connected with the analog voltage AVDD, the drain electrode of the PMOS tube MP1 is respectively and electrically connected with the drain electrode of the NMOS tube MN5 and the boost circuit, and the source electrode of the NMOS tube MN5 is grounded.
7. The low ripple charge pump circuit of claim 5, wherein the boost control circuit comprises an NMOS tube MN0, an NMOS tube MN1, a capacitor C0 and a capacitor C1, wherein the sources of the NMOS tube MN0 and the NMOS tube MN1 are respectively connected with an input voltage VIN, the grid electrode of the NMOS tube MN0 is respectively electrically connected with the drain electrode of the NMOS tube MN1 and the upper electrode plate of the capacitor C1 and then used as a first output end of the boost control circuit for outputting a first boost control signal, the lower electrode plate of the capacitor C1 is electrically connected with the first clock input end of the charge pump main body circuit for accessing the first clock signal CLK_1, the grid electrode of the NMOS tube MN1 is respectively electrically connected with the drain electrode of the NMOS tube MN0 and the upper electrode plate of the capacitor C0 and then used as a second output end of the boost control circuit for outputting a second boost control signal, and the lower electrode plate of the capacitor C0 is electrically connected with the second clock input end of the charge pump main body circuit for accessing the second clock signal CLK_2.
8. The low-ripple charge pump circuit of claim 5, wherein the boost circuit comprises an NMOS tube MN2, an NMOS tube MN3, a capacitor C2 and a capacitor C3, wherein sources of the NMOS tube MN2 and the NMOS tube MN3 are connected with an input voltage VIN, a grid electrode of the NMOS tube MN3 is used as a first input end of the boost circuit and connected with a first output end of the boost circuit after being electrically connected with an upper polar plate of the capacitor C3, a lower polar plate of the capacitor C3 is electrically connected with a reverse circuit, a grid electrode of the NMOS tube MN2 is used as a second input end of the boost circuit and connected with a second boost control signal, a drain electrode of the NMOS tube MN2 is used as a second output end of the boost circuit after being electrically connected with an upper polar plate of the capacitor C2 and connected with a lower polar plate of the capacitor C2, and the lower polar plate of the capacitor C2 is electrically connected with the reverse circuit.
9. The low-ripple charge pump circuit of claim 5, wherein the output control circuit comprises a PMOS tube MP6, a PMOS tube MP7, a capacitor C4 and a capacitor C5, wherein sources of the PMOS tube MP6 and the PMOS tube MP7 are connected with a charge pump output voltage VOUT0, grid electrodes of the PMOS tube MP6 are respectively electrically connected with drain electrodes of the PMOS tube MP7 and an upper electrode plate of the capacitor C5 and then used as a first output end of the output control circuit to output a first output control signal, a lower electrode plate of the capacitor C5 is electrically connected with the reversing circuit, grid electrodes of the PMOS tube MP7 are respectively electrically connected with drain electrodes of the PMOS tube MP6 and an upper electrode plate of the capacitor C4 and then used as a second output end of the output control circuit to output a second output control signal, and a lower electrode plate of the capacitor C4 is electrically connected with the reversing circuit.
10. The low-ripple charge pump circuit of claim 5, wherein the output circuit comprises a PMOS tube MP2, a PMOS tube MP3, a PMOS tube MP4 and a PMOS tube MP5, wherein the grid electrode of the PMOS tube MP2 and the grid electrode of the PMOS tube MP3 are electrically connected with the first output end of the output control circuit and used for being connected with a first output control signal, and the drain electrode of the PMOS tube MP2 and the drain electrode of the PMOS tube MP3 are electrically connected and then used as the first input end of the output circuit and used for being connected with a first boost signal; the grid electrode of the PMOS tube MP4 and the grid electrode of the PMOS tube MP5 are electrically connected with the second output end of the output control circuit and used for being connected with a second output control signal, and the drain electrode of the PMOS tube MP4 and the drain electrode of the PMOS tube MP5 are electrically connected and then used as the second input end of the output circuit and used for being connected with a second boost signal; The source electrode of the PMOS tube MP3 and the source electrode of the PMOS tube MP5 are electrically connected and then serve as a first output end of the output circuit and are used for outputting a charge pump output voltage VOUT0, and the substrates of the PMOS tube MP2, the PMOS tube MP3, the PMOS tube MP4 and the PMOS tube MP5 are electrically connected with the source electrode of the PMOS tube MP2 and the source electrode of the PMOS tube MP4 and then serve as a second output end of the output circuit and are used for outputting a dynamic substrate bias voltage VOUT1.

Description

Low ripple charge pump circuit Technical Field The invention belongs to the field of semiconductor memory circuits, and particularly relates to a low-ripple charge pump circuit. Background As semiconductor technology moves into more advanced nodes, the operating voltage of integrated circuits continues to be lower, while modules such as OTP (one time programmable) memories still require higher programming voltages to ensure reliable writing of data. Although the traditional charge pump circuit has a boosting function, the technical limitation of the traditional charge pump circuit is increasingly prominent in a low power supply voltage environment. The circuit mostly adopts a basic voltage doubling structure, the output voltage of the circuit is easily influenced by device parameters and process deviation, the boosting efficiency is low, and the output stability is insufficient. In particular, under deep submicron processes, it is often difficult for conventional charge pumps to generate sufficiently high and stable programming voltages, subject to physical parameters such as device threshold voltages. In addition, the output voltage of existing charge pump designs is typically large in ripple, which directly affects the programming accuracy and reliability of the OTP memory. During programming, if the supply voltage fluctuates, the memory cells may be in non-ideal programming states, which may affect the performance uniformity of the entire memory array. Meanwhile, the output voltage regulation capability of the traditional charge pump is limited, and the specific requirements of the OTP memory on the programming voltage under different process conditions are difficult to flexibly adapt. Therefore, it is desirable to develop a novel low-ripple, high-stability charge pump circuit that can still provide stable and reliable high-voltage output under the condition of extremely low supply voltage, so as to meet the accurate programming requirement of the OTP memory under advanced process nodes. Disclosure of Invention Aiming at the defects of the prior art, the invention aims to provide a low-ripple charge pump circuit. In order to solve the technical problems, the invention provides the following technical scheme: a low ripple charge pump circuit, comprising A non-overlapping clock circuit for generating a first clock signal CLK_1 and a second clock signal CLK_2 which are non-overlapping based on an external clock signal CLK, and The charge pump body circuit is used for boosting the input voltage VIN according to the first clock signal CLK_1 and the second clock signal CLK_2 to form a charge pump output voltage VOUT0 and a dynamic substrate bias voltage VOUT1. Further, the non-overlapping clock circuit comprises an inverter INV1, a NAND gate NAND2, a buffer BUF1, a buffer BUF2, a first phase delay unit and a second phase delay unit, wherein the first phase delay unit and the second phase delay unit are used for carrying out phase delay on an input signal and outputting the input signal; The input end of the inverter INV1 and the second input end of the NAND gate NAND2 are electrically connected with the input end of the non-overlapping clock circuit and are used for accessing an external clock signal CLK; The first input end of the NAND gate NAND1 is electrically connected with the output end of the first phase delay unit, and the output end of the NAND gate NAND1 is electrically connected with the input end of the second phase delay unit and the input end of the buffer BUF1 respectively; The first input end of the NAND gate NAND2 is electrically connected with the output end of the second phase delay unit, the output end of the NAND gate NAND2 is electrically connected with the input end of the first phase delay unit and the input end of the buffer BUF2 respectively, and the output end of the buffer BUF2 is electrically connected with the second output end of the non-overlapping clock circuit and is used for outputting a second clock signal CLK_2. Further, the first phase delay unit comprises an inverter INV2, an inverter INV3, an inverter INV4 and a NAND gate NAND3, wherein the input end of the inverter INV2 is electrically connected with the first input end of the NAND gate NAND3 and then used as the input end of the first phase delay unit, the output end of the inverter INV2 is electrically connected with the input end of the inverter INV3, the output end of the inverter INV2 is electrically connected with the second input end of the NAND gate NAND3, the output end of the NAND gate NAND3 is electrically connected with the input end of the inverter INV4, and the output end of the inverter INV4 is used as the output end of the first phase delay unit. Further, the second phase delay unit comprises an inverter INV5, an inverter INV6, an inverter INV7 and a NAND gate NAND4, wherein the input end of the inverter INV5 is electrically connected with the first input end of the NAND gate NAND4 and then used as the i