CN-121999820-A - Field programmable memory array, writing method and reading method

CN121999820ACN 121999820 ACN121999820 ACN 121999820ACN-121999820-A

Abstract

The invention provides a field programmable memory array, a writing method and a reading method, the field programmable memory array includes a single readable and writable memory array, an address circuit and an access circuit. The readable and writable memory array includes m memory cells of 2 i columns and 2 j rows to perform digital circuit functions and features a plurality of digital inputs and a plurality of digital outputs, and the addressing circuit is configured to receive an n-bit input vector and is coupled between the readable and writable memory array and the access circuit. The n-bit input vector is selected from a register conversion layer logic table, and the logic table comprises a plurality of n-bit input vectors and a plurality of m-bit output vectors. FPMA utilizes the word line/bit line multiplexer characteristics of a memory array to perform multiple binary inputs and any number of multiple binary outputs. The FPMA has the advantages of reducing the connection complexity and the number of repeated flip-flops, and saving the area of a crystal grain in an integrated circuit chip.

Inventors

WANG LIZHONG
WANG DARUI

Assignees

芯立嘉集成电路(上海)有限公司

Dates

Publication Date: 20260508
Application Date: 20260206

Claims (15)

1. A field programmable memory array FPMA adapted for use in a field programmable device FPD, comprising: A readable and writable memory array comprising m memory cells of 2 i rows and 2 j columns, where n= (i+j); An access circuit including m sense amplifiers and m write drivers activated by a select signal and an enable signal, and An address circuit coupled between the access circuit and the readable and writable memory array for receiving an n-bit input vector, enabling a selected word line of the readable and writable memory array according to the enable signal, and connecting m selected bit lines of the readable and writable memory array to the access circuit; wherein the n-bit input vector is selected from a register transfer layer RTL logic table, and the RTL logic table comprises a plurality of n-bit input vectors and a plurality of m-bit output vectors with one-to-one mapping relation; Wherein when the select signal indicates a write mode and the enable signal is enabled, the m write drivers are enabled to write an m-bit output vector corresponding to the n-bit input vector to m selected memory cells in the readable and writable memory array; wherein when the select signal indicates a read mode and the enable signal is enabled, the m sense amplifiers are enabled to read the voltage signals of the m selected memory cells to output the m-bit output vector, wherein m, n, i, and j >0, and Wherein the locations of the m selected memory cells are related to the selected word line and the m selected bit lines.
2. The FPMA according to claim 1, further comprising: an m-bit input/output register circuit coupled to the access circuit and enabled by the select signal and the enable signal; Wherein when the select signal indicates the write mode and the enable signal is enabled, the m write drivers are enabled to write the m-bit output vector stored in the m-bit output/input register circuit to the m selected memory cells, and When the selection signal indicates the read mode and the enable signal is activated, the m sense amplifiers are activated to read the voltage signals of the m selected memory cells and store the voltage signals to the m-bit output/input register circuit as the m-bit output vector.
3. The FPMA according to claim 1, further comprising: an n-bit input register circuit, coupled to the addressing circuit, for storing the n-bit input vector.
4. The FPMA of claim 1, wherein the n-bit input vector is partitioned into an i-bit vector and a j-bit vector, and the addressing circuitry comprises: A column circuit for decoding the i-bit vector into the selected word line and activating the selected word line, and And a row selector for decoding the j-bit vector into a selected row and connecting the m selected bit lines and the access circuit according to the selected row.
5. The FPMA of claim 1, wherein the readable and writable memory array is selected from a group comprising an SRAM array, a DRAM array, and a non-volatile RAM array.
6. A method of writing an m-bit output vector into a field programmable memory array FPMA of a field programmable device, the FPMA comprising an access circuit, an addressing circuit, and a readable and writable memory array comprising 2 i columns and 2 j rows of m memory cells, wherein the addressing circuit is coupled between the access circuit and the readable and writable memory array, the method comprising: A receiving step of receiving an n-bit input vector in a register transfer layer RTL logic table by the addressing circuit to select a word line and connecting m selected bit lines of the readable and writable memory array to the access circuit, and An activation step of activating the selected word line with the addressing circuit and activating m write drivers in the access circuit to write the m-bit output vector corresponding to the n-bit input vector into m selected memory cells of the readable and writable memory array according to the selected word line and the m selected bit lines; Wherein the RTL logic table comprises a plurality of n-bit input vectors and a plurality of m-bit output vectors with one-to-one mapping relation, and Where n= (i+j), and m, n, i, and j > 0.
7. The method of claim 6, further comprising: Storing the m-bit output vector in an m-bit input/output register circuit prior to the enabling step, wherein the m-bit input/output register circuit is enabled by a select signal and the select signal indicates a write mode; wherein the FPMA further comprises the m-bit input/output register circuit coupled to the access circuit.
8. The method of claim 6, further comprising: Storing the n-bit input vector in an n-bit input register circuit prior to the receiving step, and Dividing the n-bit input vector into an i-bit vector and a j-bit vector; Wherein the FPMA further comprises the n-bit input register circuit coupled to the addressing circuit.
9. The method of claim 8, wherein the receiving step comprises: Decoding the i-bit vector into the selected word line with the addressing circuit; Decoding the j-bit vector into a selected column with the addressing circuit, and The m selected bit lines are connected to the m write drivers by the addressing circuit according to the selected column.
10. The method of claim 6, wherein the readable and writable memory array is selected from the group consisting of an SRAM array, a DRAM array, and a non-volatile RAM array.
11. A method of reading an m-bit output vector from a field programmable memory array, FPMA, of a field programmable device, the FPMA including an access circuit, an addressing circuit, and a readable and writable memory array, the readable and writable memory array including 2 i columns and 2 j rows of m memory cells, and a plurality of m-bit output vectors having been pre-stored and selected from a register transfer layer, RTL, logic table, wherein the addressing circuit is coupled between the access circuit and the readable and writable memory array, the method comprising: A receiving step of receiving an n-bit input vector in the RTL logic table with the addressing circuit to select a word line and connect m selected bit lines of the readable and writable memory array with the access circuit, and An activation step of activating a selected word line with the addressing circuit and activating m sense amplifiers in the access circuit to read a plurality of voltage signals from m selected memory cells of the readable and writable memory array according to the selected word line and the m selected bit lines to output the m-bit output vector corresponding to the n-bit input vector; Wherein the RTL logic table comprises a plurality of n-bit input vectors and a plurality of m-bit output vectors having a one-to-one mapping relationship, and Where n= (i+j), and m, n, i, and j > 0.
12. The method of claim 11, wherein the step of initiating further comprises: In response to a selection signal indicating a read mode, activating an m-bit output/input register circuit to store the m-bit output vectors from the m sense amplifiers; wherein the FPMA further comprises the m-bit input/output register circuit coupled to the access circuit.
13. The method of claim 11, further comprising: Storing the n-bit input vector in an n-bit input register circuit prior to the receiving step, and Dividing the n-bit input vector into an i-bit vector and a j-bit vector; Wherein the FPMA further comprises the n-bit input register circuit coupled to the addressing circuit.
14. The method of claim 13, wherein the receiving step comprises: Decoding the i-bit vector into the selected word line with the addressing circuit; Decoding the j-bit vector into a selected column with the addressing circuit, and The addressing circuit is used for connecting the m selected bit lines and the m sense amplifiers according to the selected row.
15. The method of claim 11, wherein the readable and writable memory array is selected from the group consisting of an SRAM array, a DRAM array, and a non-volatile RAM array.

Description

Field programmable memory array, writing method and reading method Technical Field The present invention relates to a field programmable device (Field Programmable Device, FPD), an integrated circuit device for implementing digital hardware, the chip of which can be configured by the end user to implement different designs. Background FPDs offer the advantages of immediate manufacturing turn-around time, low start-up costs, low financial risk, and ease of design changes (since programming is done by the end user) for digital circuit design. The most common FPD today is an FPGA, which is based on a configuration of multiple LUTs, each LUT performing a logical operation on multiple binary inputs (typically 4 bits or 6 bits) and producing a single binary output (1 bit). Fig. 1 shows a schematic diagram of a typical Logic Element (LE) 100 in an FPGA using a 4-bit LUT 101. The LE 100 of FIG. 1 includes a 4-bit LUT 101 having four data inputs D 1、D2、D3、D4, a Carry circuit (Carry circuit) 102 receiving input signals (Carry input carrin) from other LEs and generating an output signal (Carry output carrout) to be output to other LEs, a Set/Clear circuit 103 responsive to two control signals Ctrl 1 and Ctrl 2 to Set/reset or Clear flip-flop 105, a Clock circuit (Clock circuit) 104 responsive to two control signals Ctrl 3 and Ctrl 4 to synchronize the operation of flip-flop 105 having a single bit data input/output, a Cascade circuit (Cascade circuit) 106 for selecting data transferred from other LEs (Cascade input CASCADE IN) or data from LUT 101 as output signal Cascade output Cascade out ' and a multiplexer 107 responsive to two control signals Ctrl 3 and Ctrl 4 to select the operation of flip-flop 105 having a single bit data input/output as output signal Cascade output signal Cascade output ' Cascade ' out ' output ' from LUT 101. Note that each LE 100 with a 4-bit input (D 1、D2、D3、D4) and a 1-bit output (LE out) requires register data "Carry out" and "Cascade out" to connect with other LEs in the LAB to implement specific logic functions, such as binary arithmetic operations or binary format conversion. To configure a LAB with multiple bit inputs and multiple bit outputs, multiple sets of LEs are required. Typically, LABs with n-bit inputs and m-bit outputs are configured with (2 n-4 ×m) LEs, where each LE contains a 4-bit input/1-bit output LUT. The connection between these (2 n-4 ×m) LEs also requires multiple memory registers to store the configuration of the LAB for n-bit inputs and m-bit outputs. Although In U.S. patent No. 11,662,980B2 (or chinese patent publication No. 113391788), an array of Read Only Memory (ROM) is used to form an In-Memory arithmetic processor (In-Memory arithmetic processors) for binary arithmetic operations. The in-memory arithmetic processor is implemented by a two-dimensional ROM memory array having an X decoder for word line selection (wordline selection) and a Y decoder for bit line multiplexer connection, and outputs a result code of an arithmetic binary operation based on two input operation element codes (op-and codes). Wherein the result code of the arithmetic binary operation is stored in a specific location of the ROM array, which location is accessed by a selected word line and a set of connected bit lines based on the two input operand codes. As shown in fig. 2 (fig. 8 of chinese patent publication 113391788), an in-memory arithmetic processor 200 includes an n-bit register (B) 210, an n-bit register (a) 220, two n-bit decoders 211 and 221, a word line driver 212, a Y-switch driver 222, a memory array 250, a Y-switch 230, and an m-bit output register (C) 240. The in-memory arithmetic processor 200 has been implemented in an integrated circuit chip and exhibits advantages of memory array compactness (taking up less silicon area) and simplicity of memory array wiring connections (word lines/bit lines) over the same arithmetic logic circuits using combinational logic gates (combinational logic gates), particularly for the logical operations of the binary code words (code words), where each binary code word contains a large number of bits. In fact, the ROM memory array converts an input binary code vector composed of two input operation element codes into a result output binary code according to arithmetic operations. Thus, the advantage of memory array compactness (taking up less silicon area) and simplicity of memory array wiring connections (word lines/bit lines) has prompted the inventors to apply readable and writable memory arrays to FPDs as FPMAs. The memory array 250 is connected to the Y-switch 230 by connecting a plurality of bit lines 25 BL. Disclosure of Invention In order to solve at least one of the above problems, the present invention provides a field programmable memory array, a writing method and a reading method. In a first aspect, the present invention provides a field programmable memory array FPMA, adapted for a field programmable device FPD, compri