CN-121999821-A - Storage device

Abstract

The present disclosure relates to a storage device. The memory device includes a cross-domain circuit including a plurality of first flip-flops that operate based on an internal clock and a plurality of second flip-flops that operate based on a data clock, the plurality of first flip-flops being initialized by a system domain reset signal, the plurality of second flip-flops being initialized by a data domain reset signal.

Inventors

• CUI ZHONGHE
• YIN XIANGZHI
• Du Jionglu
• Pu Zhengji
• PU JUNHONG

Assignees

• 爱思开海力士有限公司

Dates

Publication Date

20260508

Application Date

20250512

Priority Date

20241104

Claims (16)

1. 1. A storage device, comprising: A timing control circuit that outputs a system domain reset signal and a data domain reset signal based on a system clock, and outputs the system clock as an internal clock when the system domain reset signal is output, the output timing of the system domain reset signal being different from the output timing of the data domain reset signal, and A cross-domain circuit comprising a plurality of first flip-flops that operate based on the internal clock and a plurality of second flip-flops that are coupled to the plurality of first flip-flops and operate based on a data clock, the plurality of first flip-flops being initialized by the system domain reset signal, the plurality of second flip-flops being initialized by the data domain reset signal.
2. 2. The memory device of claim 1, wherein the cross-domain circuit requires a pipeline operation time from a time of receiving the internal clock to a time of receiving the data clock.
3. 3. The memory device according to claim 2, wherein in the timing control circuit, the output timing of the system domain reset signal is earlier than the output timing of the data domain reset signal.
4. 4. The memory device according to claim 3, wherein in the timing control circuit, the output timing of the system domain reset signal is earlier than a switching timing of the data clock by the pipe operation time.
5. 5. The memory device of claim 4, wherein the timing control circuit generates the data domain reset signal by delaying the system domain reset signal.
6. 6. The memory device of claim 5, wherein the timing control circuit generates the system domain reset signal by delaying a CAS command by a first set period of the system clock, and The data domain reset signal is generated by delaying the system domain reset signal by a second set period of the system clock, the second set period of the system clock being different from the first set period of the system clock.
7. 7. The storage device of claim 1, wherein the cross-domain circuit further comprises: A plurality of pipeline circuits that convert a first command based on the system clock to a second command based on the data clock, the data clock being based on outputs of the plurality of first flip-flops and the plurality of second flip-flops.
8. 8. The memory device of claim 7, wherein the system domain reset signal is input to a first terminal of one of the plurality of first flip-flops, and The system domain reset signal is input to second terminals of remaining ones of the plurality of first flip-flops.
9. 9. The memory device of claim 8, wherein the data field reset signal is input to a first terminal of one of the plurality of second flip-flops, and The data field reset signal is input to second terminals of remaining ones of the plurality of second flip-flops.
10. 10. The memory device of claim 9, wherein the initializing of the plurality of first flip-flops and the initializing of the plurality of second flip-flops are such that the flip-flop output of the system domain reset signal or the data domain reset signal received through the first terminal is at a level different from the levels of the remaining flip-flops.
11. 11. The memory device of claim 10, wherein the input and output structures of the first and second plurality of flip-flops are ring structures.
12. 12. A storage device, comprising: a command decoding circuit that outputs a read/write command and a CAS command synchronized with a system clock, the read/write command being read and write, the CAS command being column address strobe; A timing control circuit outputting a system domain reset signal, a data domain reset signal, and an internal clock based on the CAS command and the system clock, and outputting a delayed read/write command based on the system clock and the read/write command, and And a cross-domain circuit for synchronizing the delayed read/write command with a data clock and outputting a data input/output command, input/output being input and output, under control of the system domain reset signal, the data domain reset signal, and the internal clock.
13. 13. The memory device according to claim 12, wherein the timing control circuit further outputs the system domain reset signal at a timing earlier than an output timing of the data domain reset signal.
14. 14. The memory device of claim 13, wherein the timing control circuit further outputs the system domain reset signal based on the CAS command and the system clock, outputs the system clock as the internal clock when the system domain reset signal is output, and outputs a delayed system domain reset signal generated by delaying the system domain reset signal as the data domain reset signal.
15. 15. The memory device according to claim 14, wherein in the cross-domain circuit, a reception timing of the internal clock is earlier than a reception timing of the data clock.
16. 16. The memory device of claim 15, wherein the cross-domain circuit is further to switch the data clock after receiving the internal clock and passing a pipeline operation time.

Description

Storage device Cross Reference to Related Applications The present application claims priority from korean patent application No. 10-2024-0154294, filed on month 4 11 of 2024, which is incorporated herein by reference in its entirety. Technical Field Embodiments of the present disclosure relate to integrated circuit technology, and more particularly, to a memory device. Background Recently, with miniaturization, low power consumption, high performance, diversification, and the like of electronic devices, there is a demand for a storage device capable of storing information in a variety of electronic devices such as computers and portable communication devices. In order to achieve high performance, a storage device for inputting and outputting data at high speed is being developed to use a system clock for receiving addresses and commands and a data clock for inputting and outputting data. Thus, a memory device using heterogeneous clocks requires a cross-domain circuit capable of synchronizing heterogeneous clocks. For example, a cross-domain circuit that synchronizes a command synchronized with a system clock with a data clock is required. Disclosure of Invention In one embodiment of the present disclosure, a memory device includes a timing control circuit outputting a system domain reset signal and a data domain reset signal based on a system clock and outputting the system clock as an internal clock when the system domain reset signal is output, the output timing of the system domain reset signal being different from the output timing of the data domain reset signal, and a cross-domain circuit including a plurality of first flip-flops operating based on the internal clock and a plurality of second flip-flops operating based on the data clock, the plurality of first flip-flops being initialized by the system domain reset signal and the plurality of second flip-flops being initialized by the data domain reset signal. In one embodiment of the present disclosure, a memory device includes a command decoding circuit that outputs a read/write command and a CAS command synchronized with a system clock, a timing control circuit that outputs a system domain reset signal, a data domain reset signal, and an internal clock based on the CAS command and the system clock, and outputs a delayed read/write command based on the system clock and the read/write command, and a cross-domain circuit that synchronizes the delayed read/write command with the data clock under control of the system domain reset signal, the data domain reset signal, and the internal clock, and outputs a data input/output command. Drawings Fig. 1 is a diagram for describing a configuration of a storage device according to an embodiment of the present disclosure. Fig. 2 is a diagram for describing a configuration of a timing control circuit included in a memory device according to an embodiment of the present disclosure. Fig. 3 is a diagram for describing a configuration of a cross-domain circuit included in a storage device according to an embodiment of the present disclosure. Fig. 4 is a timing diagram for describing an operation of a memory device according to an embodiment of the present disclosure. Fig. 5 is a diagram for describing a configuration of a storage device according to another embodiment of the present disclosure. Fig. 6 is a diagram for describing a configuration of a timing control circuit included in a memory device according to another embodiment of the present disclosure. Fig. 7 is a diagram for describing a configuration of a cross-domain circuit included in a storage device according to another embodiment of the present disclosure. Fig. 8 is a timing diagram for describing an operation of a memory device according to another embodiment of the present disclosure. Detailed Description Various embodiments of the present disclosure relate to a memory device that provides a system clock to a cross-domain circuit at an earlier timing than a data clock. The operational reliability of the storage device can be improved. Hereinafter, embodiments according to the technical spirit of the present disclosure are described with reference to the accompanying drawings. A storage device is configured to store data and output the stored data. For example, the storage device receives a command for storing data received from an external device (e.g., a memory controller) or outputting the stored data, and receives data from the external device or outputs the stored data to the external device. In this case, the storage device receives a command in synchronization with the system clock and outputs the stored data in synchronization with the data clock. Thus, the memory device includes cross-domain circuitry for the system clock and the data clock. It should be noted that the following description relates to a cross-domain circuit included in a storage device using heterogeneous clocks, the cross-domain circuit for a system clock and a data clock is