CN-121999822-A - Redundancy control circuit, memory, redundancy control method and electronic device

Abstract

The embodiment of the disclosure provides a redundancy control circuit, a memory, a redundancy control method and an electronic device, wherein the redundancy control circuit comprises an address comparison circuit, an address control circuit and an address control circuit, wherein the address comparison circuit is configured to receive an input address and compare an M-bit signal from high to low in the input address with an M-bit signal from high to low in a fuse address according to bits to obtain M comparison signals, N comparison signals in the M comparison signals are sequentially output to the address selection circuit, the rest comparison signals except the N comparison signals are output to the address control circuit, the address selection circuit is configured to select the N comparison signals or signals of the input address corresponding to the N comparison signals as address selection signals and output to the address control circuit, and the address control circuit is configured to logically process the N address selection signals and the rest comparison signals to output whether an activation signal of a repair unit corresponding to the fuse address is activated or not.

Inventors

• Cui Junji
• KANG BOWEN

Assignees

• 北京超弦存储器研究院

Dates

Publication Date

20260508

Application Date

20241105

Claims (17)

1. 1. A redundancy control circuit configured in a memory including a normal memory area and a redundancy memory area, the redundancy control circuit comprising: The address comparison circuit is configured to receive an input address, and compare an M-bit signal from high to low in the input address with an M-bit signal from high to low in a fuse address according to bits to obtain M comparison signals, wherein N comparison signals in the M comparison signals are sequentially output to the address selection circuit, and the rest comparison signals except the N comparison signals are output to the address control circuit, wherein M is greater than or equal to 8, N is greater than or equal to 1 and less than M; the address selection circuit is configured to select the N comparison signals or the signals of the input addresses corresponding to the N comparison signals as address selection signals based on a selection control signal, and output the signals to the address control circuit; the address control circuit is configured to logically process the N address selection signals and the remaining comparison signals to output an activation signal of whether to activate a repair unit corresponding to the fuse address.
2. 2. The redundant control circuit of claim 1, wherein, The repair unit corresponding to the fuse address includes a number of redundant address lines related to a number of signals of the input address among the N address selection signals.
3. 3. The redundant control circuit of claim 1, wherein, When the number of the input address signals in the N address selection signals is X, the number of redundant address lines included in the repair unit corresponding to the fuse address is 2 X+1 , and X is 0 or more.
4. 4. The redundant control circuit of claim 1, wherein, The address comparison circuit comprises M exclusive-OR gates, wherein a first input end of each exclusive-OR gate receives a signal of one bit of the input address, a second input end of each exclusive-OR gate receives a signal of the fuse address corresponding to the input address, and an output end of each exclusive-OR gate outputs the comparison signal.
5. 5. The redundant control circuit of claim 4, wherein, The address selection circuit comprises N data selectors, wherein a first input end of each data selector receives one comparison signal, a second input end of each data selector receives a signal of a corresponding input address, a control end of each data selector receives the selection control signal, and an output end of each data selector outputs the address selection signal.
6. 6. The redundant control circuit of claim 5, wherein, The address control circuit comprises three stages of sub-control modules, wherein each stage of sub-control module comprises at least one logic unit; Each logic unit of the first-stage sub-control module is connected with two output ends of the address selection circuit, or each logic unit of the first-stage sub-control module is connected with one output end of the address selection circuit and one output end of the address comparison circuit, or each logic unit of the first-stage sub-control module is connected with two output ends of the address comparison circuit; each logic unit of the second-stage sub-control module is connected with the output end of one first-stage sub-control module and one fuse control signal output end; The logic unit of the third-stage sub-control module is connected with the output end of the second-stage sub-control module and one output end of the address comparison circuit.
7. 7. The redundant control circuit of claim 6, wherein, Each logic unit of the first stage sub-control module comprises a first NAND gate, wherein two input ends of the first NAND gate are respectively connected with the output ends of two data selectors, or the two input ends of the first NAND gate are respectively connected with the output ends of one data selector and the output ends of one exclusive-OR gate, or the two input ends of the first NAND gate are respectively connected with the output ends of two exclusive-OR gates.
8. 8. The redundant control circuit of claim 7, wherein, Each logic unit of the second-stage sub-control module comprises a second NAND gate, and two input ends of the second NAND gate are respectively connected with the output end of one first NAND gate and one fuse control signal output end.
9. 9. The redundant control circuit of claim 8, wherein, The logic unit of the third-stage sub-control module comprises a third NAND gate, and a plurality of input ends of the third NAND gate are respectively connected with the output ends of a plurality of second NAND gates and the output end of one exclusive-OR gate.
10. 10. A memory comprising a normal memory area, a redundant memory area, and the redundancy control circuit according to any one of claims 1 to 9.
11. 11. The memory of claim 10, wherein the memory further comprises: The fuse address storage module is used for storing an address corresponding to the abnormal address line in the normal storage area as the fuse address; The redundancy control circuit is used for comparing the input address with the fuse address to determine whether the input address is matched with the fuse address, and outputting an activation signal for activating the repair unit corresponding to the fuse address when the input address is matched with the fuse address.
12. 12. The memory of claim 11, wherein the memory is configured to store, in the memory, The address line comprises a word line and a bit line, the word line is in a ladder structure, and the fuse address is the address of the abnormal word line.
13. 13. The memory of claim 11, wherein the memory is configured to store, in the memory, The address line comprises a word line and a bit line, the bit line is of a ladder structure, and the fuse address is the address of the abnormal bit line.
14. 14. A redundancy control method configured in a memory including a normal memory area and a redundant memory area, the method comprising: Receiving an input address, and comparing an M-bit signal from high to low in the input address with an M-bit signal from high to low in a fuse address according to bits to obtain M comparison signals, wherein N comparison signals in the M comparison signals are sequentially output to an address selection circuit, and the rest comparison signals except the N comparison signals are output to an address control circuit, wherein M is more than or equal to 8, and N is more than or equal to 1 and less than M; selecting the N comparison signals or the signals of the input addresses corresponding to the N comparison signals as address selection signals based on a selection control signal; And carrying out logic processing on the N address selection signals and the rest comparison signals to output an activation signal for whether to activate the repair unit corresponding to the fuse address.
15. 15. The redundancy control method of claim 14, wherein, The repair unit corresponding to the fuse address includes a number of redundant address lines related to a number of signals of the input address among the N address selection signals.
16. 16. The redundancy control method of claim 14, wherein, When the number of the input address signals in the N address selection signals is X, the number of redundant address lines included in the repair unit corresponding to the fuse address is 2 X+1 , and X is 0 or more.
17. 17. An electronic device comprising a redundant control circuit as claimed in any one of claims 1 to 9 or a memory as claimed in any one of claims 10 to 13.

Description

Redundancy control circuit, memory, redundancy control method and electronic device Technical Field The disclosure relates to the field of semiconductor technologies, and in particular, to a redundancy control circuit, a memory, a redundancy control method, and an electronic device. Background For DRAM (Dynamic Random Access Memory), dynamic random access memory) arrays, there is typically a normal (normal) memory region as well as a redundant (redundancy) memory region. In the case where the memory cells of the normal memory area cannot provide normal read-write or memory functions, such abnormal memory cells may be replaced with memory cells of the redundant memory area to ensure that the memory operates normally. As the storage density for memories increases, more redundant storage area is required to maintain the memory functioning properly. And thus a fuse array with a greater number of fuses is also required to store more addresses. Disclosure of Invention The embodiment of the disclosure provides a redundancy control circuit, a memory, a redundancy control method and electronic equipment. In a first aspect, an embodiment of the present disclosure provides a redundancy control circuit configured in a memory including a normal memory area and a redundancy memory area, the redundancy control circuit including: The address comparison circuit is configured to receive an input address, and compare an M-bit signal from high to low in the input address with an M-bit signal from high to low in a fuse address according to bits to obtain M comparison signals, wherein N comparison signals in the M comparison signals are sequentially output to the address selection circuit, and the rest comparison signals except the N comparison signals are output to the address control circuit, wherein M is greater than or equal to 8, N is greater than or equal to 1 and less than M; the address selection circuit is configured to select the N comparison signals or the signals of the input addresses corresponding to the N comparison signals as address selection signals based on a selection control signal, and output the signals to the address control circuit; the address control circuit is configured to logically process the N address selection signals and the remaining comparison signals to output an activation signal of whether to activate a repair unit corresponding to the fuse address. In some embodiments, the repair unit corresponding to the fuse address includes a number of redundant address lines related to a number of signals of the input address among the N address selection signals. In some embodiments, in a case where the signals of the input address in the N address selection signals are X, the number of redundant address lines included in the repair unit corresponding to the fuse address is 2 X+1, and X is equal to or greater than 0. In some embodiments, the address comparison circuit comprises M exclusive OR gates, wherein a first input end of each exclusive OR gate receives a signal of one bit of the input address, a second input end of each exclusive OR gate receives a signal of the fuse address corresponding to the input address, and an output end of each exclusive OR gate outputs the comparison signal. In some embodiments, the address selection circuit comprises N data selectors, a first input terminal of each data selector receives one of the comparison signals, a second input terminal of each data selector receives a signal of a corresponding input address, a control terminal of each data selector receives the selection control signal, and an output terminal of each data selector outputs the address selection signal. In some embodiments, the address control circuit comprises three stages of sub-control modules, each stage of the sub-control modules comprising at least one logic unit; Each logic unit of the first-stage sub-control module is connected with two output ends of the address selection circuit, or each logic unit of the first-stage sub-control module is connected with one output end of the address selection circuit and one output end of the address comparison circuit, or each logic unit of the first-stage sub-control module is connected with two output ends of the address comparison circuit; each logic unit of the second-stage sub-control module is connected with the output end of one first-stage sub-control module and one fuse control signal output end; The logic unit of the third-stage sub-control module is connected with the output end of the second-stage sub-control module and one output end of the address comparison circuit. In some embodiments, each logic unit of the first stage sub-control module includes a first nand gate, where two input ends of the first nand gate are respectively connected to output ends of two data selectors, or two input ends of the first nand gate are respectively connected to an output end of one data selector and an output end of one exclusive-or gate, or two input ends