CN-121999826-A - Efficient DDR low-power-consumption control method based on counter

CN121999826ACN 121999826 ACN121999826 ACN 121999826ACN-121999826-A

Abstract

The invention provides a counter-based DDR low-power-consumption efficient control method, which is applied to a low-power-consumption control module in a counter-based DDR low-power-consumption efficient control system; the method comprises the steps that a low-power-consumption control module determines a second control signal and an enable signal of the low-power-consumption state according to a first control signal of whether the low-power-consumption control module enters the low-power-consumption state, a read-write state of a DDR interface circuit and a counter enable signal, wherein the first control signal is determined by a time management module according to related parameters of the counter module, the related parameters comprise a first reference value, a second reference value, the read-write state and the counter enable signal of the counter, the second control signal and the low-power-consumption state enable signal are sent to a self-refreshing module, and the self-refreshing module determines the low-power-consumption state level of the DDR memory through a PHY chip after combining the first control signal and the read-write state of the DDR interface circuit, so that the purposes of reducing hardware resource expenditure and time sequence expenditure are achieved.

Inventors

JIANG YANDE
ZHANG RUIKANG
LI TIANLIN
MA JINGBO
HUANG CHENGLONG
ZHANG GUANGDA
DAI HUADONG
WANG HUIQUAN
HE YIBAI
FANG JIAN
ZHAO XIA

Assignees

中国人民解放军军事科学院国防科技创新研究院

Dates

Publication Date: 20260508
Application Date: 20241108

Claims (10)

1. The counter-based DDR low-power-consumption efficient control method is characterized by being applied to a low-power-consumption control module in a counter-based DDR low-power-consumption efficient control system, wherein the counter-based DDR low-power-consumption efficient control system comprises a DDR low-power-consumption controller and a DDR memory, the DDR low-power-consumption controller comprises a counter module, a time management module, a low-power-consumption control module and a self-refresh module, and the method comprises the following steps: Determining a second control signal of a low power consumption state and an enabling signal of the low power consumption state according to a first control signal of whether the low power consumption state is entered, a read-write state of the DDR interface circuit and a state enabling signal of the counter, wherein the first control signal is determined by the time management module according to related parameters of the counter module, and the related parameters of the counter module comprise a first reference value of the counter module, a second reference value of the counter module, the read-write state of the DDR interface circuit and the state enabling signal of the counter; The method comprises the steps of sending a second control signal of a low power consumption state and an enabling signal of the low power consumption state to a self-refreshing module, wherein the second control signal is used for representing coding information of low power consumption states of different levels, the second control signal of the low power consumption state and the enabling signal of the low power consumption state are used for the self-refreshing module to switch the low power consumption states of different levels according to the second control signal of the low power consumption state, the enabling signal of the low power consumption state, the first control signal and the read-write state of a DDR interface circuit, determining the low power consumption state level of the DDR memory, and then sending the low power consumption state level of the DDR memory to the DDR memory through a PHY chip.
2. The efficient control method for low power consumption of a counter-based DDR according to claim 1, wherein the determining a second control signal for a low power consumption state and an enable signal for a low power consumption state according to a first control signal for whether to enter a low power consumption state, a read-write state of the DDR interface circuit, and a state enable signal of the counter comprises: Inverting the read-write state of the DDR interface circuit to obtain a first signal; Performing AND operation on the first signal and the state enabling signal of the counter to obtain a second signal; Inverting the first control signal to obtain a third signal; Performing AND operation on the second signal and the third signal to obtain an enabling signal of the low-power consumption state; and determining a second control signal of the low power consumption state according to the first control signal, the read-write state of the DDR interface circuit and the state enabling signal of the counter.
3. The efficient control method of the DDR low power consumption based on the counter of claim 1, wherein the relevant parameters of the counter module are obtained after the counter module monitors read-write transactions of the DDR interface circuit, the read-write state of the DDR interface circuit is used for representing whether the DDR low power consumption controller receives the read-write transaction request sent by the processor, the read-write state of the DDR interface circuit is pulled down to indicate that the DDR low power consumption controller has the read-write transaction request, the read-write state of the DDR interface circuit is pulled up to indicate that the DDR low power consumption controller does not have the read-write transaction request, the state enabling signal of the counter is obtained based on the count value of the counter module, the first reference value of the counter module and the read-write state of the DDR interface circuit, and the second reference value of the counter module is used for representing the count value corresponding to the read-write state of the DDR interface circuit when the read-write state of the counter module is pulled down to pulled up.
4. The counter-based DDR low-power-consumption efficient control system is characterized by comprising a DDR low-power-consumption controller and a DDR memory, wherein the DDR low-power-consumption controller comprises a counter module, a time management module, a low-power-consumption control module and a self-refresh module; the counter module is used for monitoring read-write transactions of the DDR interface circuit to obtain relevant parameters of the counter module, wherein the relevant parameters of the counter module comprise a first reference value of the counter module, a second reference value of the counter module, a read-write state of the DDR interface circuit and a state enabling signal of the counter; The time management module is used for determining whether to enter a first control signal of a low power consumption state according to a first reference value of the counter module, a second reference value of the counter module and a read-write state of the DDR interface circuit; The low-power consumption control module is used for determining a second control signal of a low-power consumption state and an enabling signal of the low-power consumption state according to the first control signal of whether the low-power consumption state is entered, the read-write state of the DDR interface circuit and the state enabling signal of the counter; The self-refreshing module is used for determining the low power consumption state level of the DDR memory according to the second control signal of the low power consumption state, the enabling signal of the low power consumption state, the first control signal whether to enter the low power consumption state or not and the read-write state of the DDR interface circuit, and sending the low power consumption state level of the DDR memory to the DDR memory through the PHY chip, wherein the low power consumption state level of the DDR memory is used for switching the low power consumption states of different levels of the DDR memory.
5. The efficient control system for low power consumption of a counter-based DDR of claim 4, wherein said monitoring read/write transactions of a DDR interface circuit to obtain parameters associated with a counter module comprises: The method comprises the steps of monitoring read-write transaction of a DDR interface circuit, determining the read-write state of the DDR interface circuit, wherein the read-write state of the DDR interface circuit is used for representing whether the DDR has a read-write transaction request or not, the read-write state of the DDR interface circuit is pulled high to indicate that the DDR has a read-write transaction request, and the read-write state of the DDR interface circuit is pulled low to indicate that the DDR has no read-write transaction request; Under the condition that the read-write state of the DDR interface circuit is pulled down, counting is started through the counter, a count value of the counter is obtained, and whether the count value reaches a first reference value of the counter module is determined; pulling up a state enable signal of the counter when the count value of the counter reaches a first reference value of the counter module; pulling down a state enable signal of the counter if the count value does not reach a first reference value of the counter module; Determining the count value of the counter corresponding to the read-write state of the DDR interface circuit from low to high as a second reference value of the counter module; And determining the read-write state of the DDR interface circuit, the first reference value A of the counter module, the second reference value of the counter module and the state enabling signal of the counter as related parameters of the counter module.
6. The counter-based DDR low power consumption efficient control system of claim 4, wherein said time management module is further configured to: Determining whether to optimize a third control signal of the first reference value according to the first reference value of the counter module, the second reference value of the counter module and the read-write state of the DDR interface circuit, wherein the third control signal is an int_lvl signal or an lvl_en signal, the int_lvl signal is used for representing suspending the optimization of the first reference value of the counter module, and the lvl_en signal is used for representing starting the optimization of the first reference value of the counter module; under the condition that the third control signal is the lvl_en signal, optimizing the first reference value of the counter module according to the first reference value of the counter module, the second reference value of the counter module and the read-write state of the DDR interface circuit to obtain an optimized first reference value; and returning the optimized first reference value of the counter module to the counter module.
7. The counter-based DDR low-power-consumption efficient control device is characterized by being applied to a low-power-consumption control module in a counter-based DDR low-power-consumption efficient control system, wherein the counter-based DDR low-power-consumption efficient control system comprises a DDR low-power-consumption controller and a DDR memory, the DDR low-power-consumption controller comprises a counter module, a time management module, a low-power-consumption control module and a self-refresh module, and the device comprises: The system comprises a determining module, a time management module and a data processing module, wherein the determining module is used for determining a second control signal of a low power consumption state and an enabling signal of the low power consumption state according to a first control signal of a low power consumption state, a read-write state of the DDR interface circuit and a state enabling signal of the counter, wherein the first control signal is determined by the time management module according to related parameters of the counter module, and the related parameters of the counter module comprise a first reference value of the counter module, a second reference value of the counter module, the read-write state of the DDR interface circuit and the state enabling signal of the counter; The low-power-consumption state switching module is used for sending the second control signal of the low-power-consumption state and the enabling signal of the low-power-consumption state to the self-refresh module, wherein the second control signal is used for representing the coding information of the low-power-consumption state of different levels, the second control signal of the low-power-consumption state and the enabling signal of the low-power-consumption state are used for the self-refresh module to switch the low-power-consumption state of different levels according to the second control signal of the low-power-consumption state, the enabling signal of the low-power-consumption state, the first control signal and the read-write state of the DDR interface circuit, and the low-power-consumption state level of the DDR memory is used for switching the low-power-consumption state of different levels of the DDR memory after determining the low-power-consumption state level of the DDR memory through the PHY chip.
8. An electronic device comprising a memory, a processor and a computer program stored on the memory and executable on the processor, wherein the processor implements a counter-based DDR low power consumption, high efficiency control method according to any of claims 1 to 3 when executing the computer program.
9. A non-transitory computer readable storage medium having stored thereon a computer program, wherein the computer program when executed by a processor implements the counter-based DDR low power consumption, efficient control method according to any of claims 1 to 3.
10. A computer program product comprising a computer program which, when executed by a processor, implements a counter-based DDR low power consumption efficient control method as claimed in any one of claims 1 to 3.

Description

Efficient DDR low-power-consumption control method based on counter Technical Field The invention relates to the technical field of integrated circuits, in particular to a counter-based DDR low-power-consumption high-efficiency control method. Background Double data rate synchronous dynamic random access memory (Double DATA RATE SDRAM, DDR) memory is a core component of a computer system. A System on Chip (SoC) performs data transmission with a DDR memory through a DDR interface circuit. With the continuous development of integrated circuit technology, the demand of high-performance intelligent chips for DDR memory performance is continuously increasing, and DDR technology is developed towards lower power consumption, faster speed, larger capacity and smaller physical package size. In the prior art, a DDR low power consumption control logic circuit is integrated in a controller module of a DDR interface circuit. DDR memory (SDRAM) is in IDLE IDLE state when the chip has no read/write transaction, and DDR memory can enter low power consumption state to save power consumption. When the low power consumption control logic circuit does not monitor the read-write transaction in a period of time, the low power consumption control logic circuit sends a low power consumption control signal to the PHY (physical layer) module, configures a corresponding register, and then the PHY module sends a low power consumption control command to the DDR memory to enable the DDR memory to enter a low power consumption state. However, the entering into the DDR low-power control mode requires the participation of an operating system and a processor core, and the specific operation process is that the operating system sends a control command to the DDR controller of the DDR interface circuit through the processor core, and configures a register related to the DDR low-power, so that the DDR memory enters into a low-power state. Therefore, the existing DDR low power consumption control method occupies more hardware resources of a processor core and has larger time sequence cost. Disclosure of Invention The invention provides a counter-based DDR low-power-consumption high-efficiency control method, which is used for solving the defects of more hardware resources occupying a processor core and larger time sequence expenditure in the prior art and achieving the purpose of reducing the hardware resource expenditure and the time sequence expenditure. In a first aspect, the invention provides a counter-based DDR low-power-consumption efficient control method, which is applied to a low-power-consumption control module in a counter-based DDR low-power-consumption efficient control system, wherein the counter-based DDR low-power-consumption efficient control system comprises a DDR low-power-consumption controller and a DDR memory, the DDR low-power-consumption controller comprises a counter module, a time management module, the low-power-consumption control module and a self-refresh module, and the method comprises the following steps: Determining a second control signal of a low power consumption state and an enabling signal of the low power consumption state according to a first control signal of whether the low power consumption state is entered, a read-write state of the DDR interface circuit and a state enabling signal of the counter, wherein the first control signal is determined by the time management module according to related parameters of the counter module, and the related parameters of the counter module comprise a first reference value of the counter module, a second reference value of the counter module, the read-write state of the DDR interface circuit and the state enabling signal of the counter; The method comprises the steps of sending a second control signal of a low power consumption state and an enabling signal of the low power consumption state to a self-refreshing module, wherein the second control signal is used for representing coding information of low power consumption states of different levels, the second control signal of the low power consumption state and the enabling signal of the low power consumption state are used for the self-refreshing module to switch the low power consumption states of different levels according to the second control signal of the low power consumption state, the enabling signal of the low power consumption state, the first control signal and the read-write state of a DDR interface circuit, determining the low power consumption state level of the DDR memory, and then sending the low power consumption state level of the DDR memory to the DDR memory through a PHY chip. According to the high-efficiency control method of DDR low power consumption based on the counter, the method determines the second control signal of the low power consumption state and the enable signal of the low power consumption state according to the first control signal of whether to enter the low power consumption s