CN-121999828-A - Pipeline circuit and memory

Abstract

The present disclosure relates to the field of integrated circuits, and discloses a pipeline circuit and a memory. The pipeline circuit comprises a pipeline module and a delay control module. And a pipeline module configured to pipeline data and/or command address signals during reading or writing. And the delay control module is configured to control the read delay or the write delay.

Inventors

• Jin Xiujin

Assignees

• 北京超弦存储器研究院

Dates

Publication Date

20260508

Application Date

20241108

Claims (10)

1. 1. A pipeline circuit, the pipeline circuit comprising: A pipeline module configured to pipeline data and/or command address signals during a read or write process; And the delay control module is configured to control the read delay or the write delay.
2. 2. The pipeline circuit according to claim 1, wherein the delay control module comprises a plurality of delay units, and the delay units comprise timers and/or counters.
3. 3. The pipeline circuit of claim 1 wherein the pipeline module comprises a read pipeline, the delay control module comprises a read delay control module; the read delay control module is configured to receive a read command and control the read delay based on the read command; the read pipeline is configured to read the data in response to the read command.
4. 4. The pipeline circuit of claim 3 wherein the pipeline circuit is configured to control the pipeline circuit, The number of delay units in the read delay control module and the depth of the read pipeline are determined according to the upper limit of the number of the read commands.
5. 5. The pipeline circuit of claim 1, wherein the pipeline module comprises a write pipeline, and wherein the delay control module comprises a write delay control module; The writing pipeline is configured to receive a writing command, and output the writing command after format conversion, wherein the format conversion comprises encoding and/or decoding; the write delay control module is configured to receive the write command and control the write delay based on the write command.
6. 6. The pipeline circuit of claim 5 wherein the pipeline circuit is configured to control the pipeline circuit, The write pipeline comprises a memory bank group registering unit, a memory bank address registering unit, a column address registering unit and a write command registering unit, and is configured to register the format-converted command and address.
7. 7. The pipeline circuit of claim 6 wherein the pipeline circuit is configured to control the pipeline circuit, The memory bank group registering unit, the memory bank registering unit, the column address registering unit and the write command registering unit register commands and addresses according to a first-in first-out principle.
8. 8. The pipeline circuit of claim 5 wherein the pipeline circuit is configured to control the pipeline circuit, The number of delay units in the write delay control module and the depth of the write pipeline are determined according to the upper limit of the number of write commands.
9. 9. A memory comprising the pipeline circuit of any one of claims 1 to 8.
10. 10. The memory of claim 9, wherein the memory comprises at least dynamic random access memory, DRAM.

Description

Pipeline circuit and memory Technical Field The present disclosure relates to the field of integrated circuits, and in particular to a pipeline circuit and a memory. Background DRAM (Dynamic Random Access Memory ) is a semiconductor memory whose main principle of operation is to use the charge in the memory cells to characterize the stored data, i.e. whether a binary bit (bit) is a1 or a 0. DDR (double Rate synchronous dynamic random Access memory) is a DRAM with double data transfer rate, which is twice the system clock frequency, and its transfer performance is superior to that of conventional DRAM due to the increase in speed. In the peripheral circuit between the controller and the memory bank, the DDR is provided with a pipeline circuit for transmitting data or command address signals, and the pipeline circuit has room for further optimization. Disclosure of Invention In view of this, the embodiments of the present disclosure provide a pipeline circuit and a memory, which can reduce the number of components and reduce the circuit area. The technical scheme of the embodiment of the disclosure is realized as follows: The embodiment of the disclosure provides a pipeline circuit, which comprises a pipeline module and a delay control module, wherein the pipeline module is configured to carry out pipeline processing on data and/or command address signals in a reading or writing process, and the delay control module is configured to control reading delay or writing delay. In some embodiments of the present disclosure, the delay control module includes a plurality of delay units including a timer and/or a counter. In some embodiments of the present disclosure, the pipeline module includes a read pipeline, the delay control module includes a read delay control module configured to receive a read command, control the read delay based on the read command, and the read pipeline is configured to read the data in response to the read command. In some embodiments of the present disclosure, the number of delay cells in the read delay control module, and the depth of the read pipeline, are each determined according to an upper limit on the number of read commands. In some embodiments of the present disclosure, the pipeline module includes a write pipeline, the delay control module includes a write delay control module, the write pipeline is configured to receive a write command, perform format conversion on the write command and output the write command, the format conversion includes encoding and/or decoding, and the write delay control module is configured to receive the write command and control the write delay based on the write command. In some embodiments of the present disclosure, the write pipeline includes a bank group register unit, a bank address register unit, a column address register unit, and a write command register unit configured to register the format-converted command and address. In some embodiments of the present disclosure, the bank group registering unit, the bank registering unit, the column address registering unit, and the write command registering unit register commands and addresses according to a first-in first-out principle. In some embodiments of the present disclosure, the number of delay cells in the write delay control module, and the depth of the write pipeline are each determined according to an upper limit on the number of write commands. The embodiment of the disclosure also provides a memory, which comprises the pipeline circuit in the scheme. In some embodiments of the present disclosure, the memory comprises at least dynamic random access memory, DRAM. It will be appreciated that in embodiments of the present disclosure, a delay control module is employed to control the read delay or the write delay, such that there is no need to provide excessive storage elements in the pipeline to satisfy the read delay or the write delay. That is, the embodiments of the present disclosure may reduce the depth of the pipeline, that is, may reduce the number of memory elements in the pipeline, and thus, may reduce the circuit area, which may be advantageous for chip area reduction. Drawings FIG. 1 is a schematic diagram of a memory according to an embodiment of the disclosure; FIG. 2 is a schematic diagram of a pipeline circuit in the prior art; FIG. 3 is a schematic diagram of a pipeline circuit according to an embodiment of the present disclosure; FIG. 4 is a second schematic diagram of a pipeline circuit according to an embodiment of the disclosure; FIG. 5 is a third schematic diagram of a pipeline circuit according to an embodiment of the present disclosure; FIG. 6 is a schematic diagram of a pipeline circuit according to an embodiment of the present disclosure; fig. 7 is a schematic diagram of a second structure of the memory according to the embodiment of the disclosure. Detailed Description For the purpose of making the objects, technical solutions and advantages of the present disclosu