CN-121999829-A - Electronic device including memory circuit

Abstract

The present disclosure relates to a memory device including a plurality of memory cells arranged in an array having word lines and bit lines. Each cell comprises a memory element made of phase change material and two transistors connected by their first conductive nodes, which are themselves connected to the first terminal of the element. The elements of the bit line are connected by their second terminals. The two transistors of the word line are connected by their gates. Each cell is connected to two source lines, respectively, which are connected to two second nodes of the transistor. The cells of a word line are connected to two source lines, and the cells of two consecutive word lines are connected to a common source line. Each transistor is disposed in and on a pair of two fins disposed in the semiconductor substrate.

Inventors

• O. WEBER

Assignees

• 意法半导体国际公司

Dates

Publication Date

20260508

Application Date

20251104

Priority Date

20241107

Claims (20)

1. 1. A memory device, comprising: a plurality of memory cells arranged in an array having word lines and bit lines, each memory cell comprising: A memory element of phase change material comprising a first terminal and a second terminal, and Two fin field effect transistors for selecting the memory element, each transistor comprising a first conductive node and a second conductive node and a gate, wherein: two transistors of the same memory cell are connected to each other by their first conductive nodes, which are connected to a first terminal of the memory element; the memory elements of the same bit line are all connected to each other by their second terminals; The two transistors of the memory cells of the same word line are all connected to each other by their gates; Each memory cell is connected to two source lines connected to two second conductive nodes of the transistors of the memory cells, respectively, the memory cells of the same word line are connected to two same source lines, and the memory cells of two consecutive word lines are connected to a common source line, and Each transistor is disposed in and on a pair of two parallel and adjacent fins disposed in the semiconductor substrate.
2. 2. The memory device of claim 1, wherein the transistors of the memory cells of a same bit line are disposed on and in a same pair of two fins.
3. 3. The memory device of claim 1, wherein the fins in the same pair are spaced 20nm to 25nm apart.
4. 4. The memory device of claim 1, wherein the fin pairs of the memory cells in and on which two consecutive bit lines are disposed are spaced 60nm to 65nm apart.
5. 5. The memory device of claim 1, wherein the phase change material is made of an alloy of germanium, antimony, and tellurium.
6. 6. The memory device of claim 1, wherein within each memory cell, the memory element is separated from the transistor by an interconnect stack.
7. 7. The memory device of claim 6, wherein each memory element is connected to the first conductive node of two transistors of a same memory cell by a conductive via through the interconnect stack.
8. 8. The memory device of claim 1, wherein the memory element comprises a heating metal resistance element disposed below and controlling the phase change material.
9. 9. The memory device of claim 1, wherein the source line is parallel to a word line in a top view.
10. 10. The memory device of claim 1, wherein the fins are disposed in a first region of the semiconductor substrate, The apparatus also includes regularly spaced other fins disposed in the second region of the semiconductor substrate.
11. 11. The memory device of claim 1, wherein fins in a same pair are closer than fins in two adjacent pairs.
12. 12. A method for manufacturing a device comprising a plurality of memory cells arranged in an array with word lines and bit lines, each memory cell comprising a memory element made of a phase change material and two fin field effect transistors for selecting the memory element, each transistor comprising a first conductive node and a second conductive node and a gate, the memory element comprising two terminals, wherein: two transistors of the same memory cell are connected to each other by their first conductive nodes, which are connected to a first terminal of the memory element; the memory elements of the same bit line are all connected to each other by their second terminals; Two transistors of the memory cell in the same word line are all connected to each other by their gates; Each memory cell is connected to two source lines, which are connected to two second conductive nodes of the transistors of the memory cells, respectively, the memory cells of the same word line are connected to two same source lines, and the memory cells of two consecutive word lines are connected to a common source line, The method comprises the following steps: forming fins in the semiconductor substrate, wherein the fins are formed in pairs; epitaxially forming a semiconductor layer, and The semiconductor layer is doped to form a plurality of regions in which a first region corresponds to a source region and a second region corresponds to a drain region, the drain region being common to two transistors of a same memory cell and the source region being common to two transistors of two adjacent memory cells.
13. 13. The method of claim 12 wherein the forming of the fins is performed in a first region of the semiconductor substrate, The method further includes forming additional regularly spaced fins in the second region of the semiconductor substrate during the fin forming step.
14. 14. The method of claim 12, wherein the fins in the same pair are closer together than the fins in two adjacent pairs.
15. 15. A method, comprising: In a memory array comprising a plurality of memory cells arranged in a plurality of bit lines and a plurality of word lines, a first non-zero potential being applied on a first bit line of the plurality of bit lines of the memory array and zero potentials being applied on other bit lines of the plurality of bit lines of the memory array, each memory cell comprising a memory element of phase change material and two fin field effect transistors for selecting the memory element, the memory element comprising a first terminal and a second terminal, each transistor comprising a first conductive node and a second conductive node and a gate, wherein: two transistors of the same memory cell are connected to each other by their first conductive nodes, which are connected to a first terminal of the memory element; the memory elements of the same bit line are all connected to each other by their second terminals; The two transistors of the memory cells of the same word line are all connected to each other by their gates; Each memory cell is connected to two source lines connected to two second conductive nodes of the transistors of the memory cells, respectively, the memory cells of the same word line are connected to two same source lines, and the memory cells of two consecutive word lines are connected to a common source line, and Each transistor is arranged in and on a pair of two parallel and adjacent fins arranged in the semiconductor substrate; applying a second non-zero potential on a first word line of the plurality of word lines and zero potential on other word lines of the plurality of word lines; a zero potential is applied to two source lines of the memory cells coupled to the first word line and a third non-zero potential is applied to the other source lines.
16. 16. The method of claim 15, wherein the transistors of the memory cells of a same bit line are disposed on and in a same pair of two fins.
17. 17. The method of claim 15, wherein the fins in the same pair are spaced 20nm to 25nm apart.
18. 18. The method of claim 15, wherein the fin pairs of the memory cells in and on which two consecutive bit lines are disposed are spaced 60nm to 65nm apart.
19. 19. The method of claim 15, wherein the phase change material is made of an alloy of germanium, antimony, and tellurium.
20. 20. The method of claim 16, wherein the fins in the same pair are closer together than the fins in two adjacent pairs.

Description

Electronic device including memory circuit Cross Reference to Related Applications The present application claims priority from French patent application FR2412188 entitled "Dispositif e lectronique comprenant un circuit m e Moire", filed on 7.11.2024, which is incorporated herein by reference to the maximum extent allowed by law. Technical Field The present description relates generally to electronic devices, and more particularly to electronic devices that include memory circuitry. Background The electronic device includes both memory circuitry and logic circuitry. Of more particular interest herein are electronic devices (referred to as memory devices) that include memory circuitry that includes memory elements arranged in an array, each memory element being associated with one or more select transistors. The transistor is used to program, erase or read each memory element separately. It is desirable to at least partially improve some aspects of known electronic devices. Disclosure of Invention To this end, one embodiment provides a memory device comprising a plurality of memory cells arranged in an array having word lines and bit lines, each memory cell comprising a memory element made of a phase change material and two fin field effect transistors for selecting the memory element, each transistor comprising a first conductive node and a second conductive node and a gate, the memory element comprising two terminals, wherein: Two transistors of the same memory cell are connected to each other by a first conductive node thereof, said first conductive node being connected to a first terminal of the memory element; The memory elements of the same bit line are all connected to each other through their second terminals; The two transistors of the memory cells of the same word line are all connected to each other by their gates; each memory cell is connected to two source lines, the two source lines are respectively connected to two second conductive nodes of transistors of the memory cells, memory cells of the same word line are connected to two same source lines, and memory cells of two consecutive word lines are connected to a common source line, and Each transistor is disposed in and on a pair of two parallel and adjacent fins disposed in the semiconductor substrate. According to one embodiment, the transistors of the memory cells of the same bit line are disposed on and in the same pair of two fins. According to one embodiment, the fins in the same pair are spaced 20nm to 25nm apart, for example about 22nm. According to one embodiment, pairs of fins in and on which two consecutive bit line memory cells are disposed are spaced 60nm to 65nm apart, for example about 62nm apart. According to one embodiment, the phase change material is made of an alloy of germanium, antimony and tellurium. According to one embodiment, within each memory cell, the memory element is separated from the transistor by an interconnect stack. According to one embodiment, each memory element is connected to the first conductive node of two transistors of the same memory cell by a conductive via through the interconnect stack. According to one embodiment, a memory element includes a heating metal resistance element disposed below and controlling a phase change material. According to one embodiment, the source lines are parallel to the word lines in a top view. According to one embodiment, the fins are disposed in a first region of the semiconductor substrate, The apparatus also includes regularly spaced other fins disposed in the second region of the semiconductor substrate. Another embodiment provides a method of manufacturing a device, the apparatus comprising a plurality of memory cells arranged in an array having word lines and bit lines, each memory cell comprising a memory element made of a phase change material and two fin field effect transistors for selecting the memory element, each transistor comprising a first conductive node and a second conductive node and a gate, the memory element comprising two terminals, wherein: Two transistors of the same memory cell are connected to each other by a first conductive node thereof, said first conductive node being connected to a first terminal of the memory element; The memory elements of the same bit line are all connected to each other through their second terminals; Two transistors of a memory cell in the same word line are all connected to each other through their gates; Each memory cell is connected to two source lines, the two source lines are respectively connected to two second conductive nodes of transistors of the memory cells, memory cells of the same word line are connected to two same source lines, and memory cells of two consecutive word lines are connected to a common source line, The method comprises the following steps: forming fins in the semiconductor substrate, wherein the fins are formed in pairs; epitaxially forming a semiconductor layer, and The semiconductor l