CN-121999830-A - 2T0C DRAM read-write method and system for multi-value storage

CN121999830ACN 121999830 ACN121999830 ACN 121999830ACN-121999830-A

Abstract

The invention discloses a 2T0C DRAM read-write method and system for multi-value storage, which relates to the technical field of multi-value storage, and the method comprises the steps of adopting a multi-value current source to transmit preset write currents matched with data to be written to all target storage units needing to be written with the same data to be written in a 2T0C DRAM storage array; the method comprises the steps of enabling a writing transistor and a reading transistor in target memory cells to share the same bit line, enabling all the target memory cells to adaptively generate respective storage node voltages based on preset writing currents and combining threshold voltages of the respective reading transistors to enable overdrive voltages of all the target memory cells to be the same, enabling the overdrive voltages to uniquely correspond to data to be written, detecting reading currents on the bit line to obtain storage data when the data are read, and enabling the reading currents to be uniquely determined by the overdrive voltages. The method is used for solving the problem that the influence of threshold voltage fluctuation on multi-value storage accuracy in the traditional technology is solved in the prior art.

Inventors

Mao Naide
YANG GUANHUA
Liu Menggan
CHEN KAIFEI
LIAO FUXI
LI ZIHAN
ZHANG XUANMING
LI LING

Assignees

中国科学院微电子研究所

Dates

Publication Date: 20260508
Application Date: 20260121

Claims (9)

1. The 2T0C DRAM read-write method for multi-value storage is characterized by comprising the following steps: A multi-value current source is adopted to transmit a preset write current matched with the data to be written to all target storage units needing to be written with the same data to be written in a 2T0C DRAM storage array, wherein a write transistor and a read transistor in the target storage units share the same bit line; all target memory cells adaptively generate respective storage node voltages by combining threshold voltages of respective reading transistors based on the preset write current to enable overdrive voltages of all target memory cells to be the same; When data is read, the read current on the bit line is detected to obtain the stored data, and the read current is uniquely determined by the overdrive voltage.
2. The 2T0C DRAM read/write method for multi-value storage according to claim 1, wherein said preset write current and said overdrive voltage form a constraint relation; All the target memory cells adaptively generate respective storage node voltages in combination with threshold voltages of respective read transistors based on the preset write currents so that overdrive voltages of the target memory cells are the same, including: Based on the constraint relation, the target storage units with different threshold voltages among all the target storage units adaptively adjust the storage node voltage of the target storage units through the storage nodes, so that the overdrive voltages of all the target storage units are the same.
3. The multi-value storage oriented 2t0c DRAM read/write method of claim 2, wherein the constraint relationship is a transistor current formula: Wherein, the ; -Providing a voltage to said storage node; A gate-source voltage for the write transistor; For the preset write current; Is carrier mobility; the capacitance of the lower gate oxide layer is the unit area; Is the channel width-to-length ratio; Is the channel width; Is the channel length; Is the threshold voltage of the read transistor.
4. The 2t0c DRAM read/write method for multi-value storage of claim 2, wherein the drain of the write transistor and the drain of the read transistor are commonly connected to the bit line and the bit line is directly connected to the multi-value current source; The source electrode of the writing transistor is connected with the storage node; the source electrode of the reading transistor is connected with a reading word line and the reading word line is always grounded; Adopting a multi-value current source to transmit a preset write current matched with the data to be written to all target memory cells to be written with the same data to be written in a 2T0C DRAM memory array, comprising: Applying a preset high level to the write word line to turn on the write transistor; Transmitting the preset write current through the bit line using the multi-value current source; and after the preset write current flows in through the drain electrode of the write-in transistor and flows out through the source electrode of the write-in transistor, the write-in current flows to the storage node of the target storage unit, and when the storage node is charged, a current path of the write-in transistor is turned off, so that the drain current of the read-in transistor is equal to the preset write-in current.
5. The multi-value storage oriented 2t0c DRAM read/write method of claim 4, wherein prior to detecting a read current on a bit line to obtain stored data, the method further comprises: After the data writing is completed, the writing word line is set to be at a preset low level, so that the writing transistor is turned off, and a current signal connected with the bit line is converted into a voltage signal.
6. The multi-value storage-oriented 2t0c DRAM read/write method according to claim 1, wherein the multi-value current source comprises Each independent current branch outputs a discrete current value within a preset range, each discrete current value corresponds to a multi-value storage state, the corresponding current branch is selected to input matched current to the corresponding target storage unit, For the number of bits stored in multiple values, Greater than or equal to 1.
7. The 2t0c DRAM read/write method for multi-value storage according to claim 6, wherein the preset range of discrete current values outputted by the multi-value current source is 100pA to 3 μa.
8. The 2t0c DRAM read/write method for multi-value storage according to claim 1, wherein the multi-value current source is realized by a semiconductor parameter tester and a probe station in a common simulation; After being generated by the semiconductor parameter tester, a write current signal is applied to the corresponding bit line through the probe station; And the read current signal on the bit line is conducted to the semiconductor parameter testing machine through the probe station, the read current signal is detected by the testing machine, and the storage data of the target storage unit are obtained by combining a preset current data mapping relation.
9. The 2T0C DRAM read-write system for multi-value storage is characterized by comprising a multi-value current source, a 2T0C DRAM storage array and a read detection module; The 2T0C DRAM memory array comprises a plurality of memory cells arranged in an array form; Each memory cell comprises a writing transistor and a reading transistor, and the writing transistor and the reading transistor share the same bit line; Each bit line is respectively connected with the multi-value current source and the reading detection module; The multi-value current source is used for transmitting a preset write current matched with the data to be written to all target storage units which need to be written with the same data to be written in the 2T0C DRAM storage array; each target memory cell is used for adaptively generating a storage node voltage based on the preset write current and the threshold voltage of the self-reading transistor so as to keep the overdrive voltage of each target memory cell consistent, and the overdrive voltage uniquely corresponds to the data to be written; the read detection module is used for detecting the read current on the bit line to obtain the stored data when the data is read, and the read current is uniquely determined by the overdrive voltage.

Description

2T0C DRAM read-write method and system for multi-value storage Technical Field The invention relates to the technical field of multi-value storage, in particular to a 2T0C DRAM read-write method and system for multi-value storage. Background In the technical field of semiconductor memory, a dynamic random access memory (Dynamic Random Access Memory, DRAM) is an indispensable core memory component in various electronic devices by virtue of high read-write speed and good compatibility. Among them, the DRAM of the 2T0C structure is receiving attention from a multi-value memory scenario due to potential advantages in terms of area utilization and integration. The multi-value storage technology can enable a single storage unit to bear data with more than 1 bit, compared with the traditional binary storage, the storage density can be greatly improved under the same storage unit number, and the urgent requirement of the current electronic equipment on mass storage is met. However, the conventional 2t0c DRAM adopts the voltage writing method, which faces serious challenges in practical application. Because of non-ideal factors such as non-uniform film growth thickness of a channel or a gate dielectric and the like, limited etching process precision and the like in the preparation process of the device, the threshold voltages of different DRAM memory cells can inevitably fluctuate. In the conventional voltage writing mechanism, the voltage of the storage node is raised to the same level as the voltage of the bit line during writing, and the reading operation depends on the magnitude of the current of the read bit line to determine the voltage state of the storage node, so as to determine the stored data. However, the fluctuation of the threshold voltage can significantly influence the value of the read current, so that the multi-value levels of different memory cells are mutually interfered, the specific memory states cannot be accurately distinguished, and the application feasibility of the 2T0C DRAM in the multi-value memory field is severely restricted. Disclosure of Invention The invention aims to provide a 2T0C DRAM read-write method and system for multi-value storage, which are used for solving the influence of threshold voltage fluctuation on multi-value storage accuracy in the traditional technology. In order to achieve the above object, the present invention provides the following technical solutions: In a first aspect, the present invention provides a 2t0c DRAM read/write method for multi-value storage, which is characterized by comprising: A multi-value current source is adopted to transmit a preset write current matched with the data to be written to all target memory cells needing to be written with the same data to be written in a 2T0C DRAM memory array; All target memory cells adaptively generate respective storage node voltages by combining threshold voltages of respective reading transistors based on preset write currents to enable overdrive voltages of all target memory cells to be the same; when reading data, the reading current on the bit line is detected to obtain the stored data, and the reading current is uniquely determined by the overdrive voltage. Optionally, the preset write current and the overdrive voltage form a constraint relation, wherein the overdrive voltage is the difference value between the voltage of the storage node and the threshold voltage; all target memory cells adaptively generate respective storage node voltages in combination with threshold voltages of respective read transistors based on a preset write current so that overdrive voltages of the respective target memory cells are the same, comprising: Based on the constraint relation, the target storage units with different threshold voltages among all the target storage units adaptively adjust the storage node voltage of the target storage units through the storage nodes, so that the overdrive voltages of all the target storage units are the same. Optionally, the constraint relationship is a transistor current formula: ; Wherein, the ;Is the storage node voltage; A gate-source voltage for the write transistor; is a preset write current; Is carrier mobility; the capacitance of the lower gate oxide layer is the unit area; Is the channel width-to-length ratio; Is the channel width; Is the channel length; Is the threshold voltage of the read transistor. Optionally, the drain of the writing transistor and the drain of the reading transistor are connected to the bit line, and the bit line is directly connected with the multi-value current source; The source electrode of the reading transistor is connected with a reading word line and is always grounded; Adopting a multi-value current source to transmit a preset write current matched with the data to be written to all target memory cells to be written with the same data to be written in a 2T0C DRAM memory array, comprising: Applying a preset high level to the write word