CN-121999831-A - Memory device

Abstract

A memory device includes a first memory cell array including a plurality of bit lines, a second memory cell array including a plurality of complementary bit lines corresponding to the plurality of bit lines and disposed adjacent to the first memory cell array in a first direction, and a first bit line sense amplifier array having at least a portion overlapping the first memory cell array on the first memory cell array and including a plurality of first bit line sense amplifiers connected to a plurality of first bit lines among the plurality of bit lines and a plurality of first complementary bit lines among the plurality of complementary bit lines.

Inventors

• XU DEYONG
• JIANG KUIZHANG

Assignees

• 三星电子株式会社

Dates

Publication Date

20260508

Application Date

20250620

Priority Date

20241107

Claims (20)

1. 1. A memory device, the memory device comprising: A first memory cell array including a plurality of bit lines; A second memory cell array including a plurality of complementary bit lines corresponding to the plurality of bit lines, respectively, wherein the second memory cell array is arranged adjacent to the first memory cell array in a first lateral direction, and A first bit line sense amplifier array at least partially overlapping the first memory cell array in a vertical direction, wherein the first bit line sense amplifier array comprises: A plurality of first bit line sense amplifiers connected to (i) a plurality of first bit lines of the plurality of bit lines and (ii) a plurality of first complementary bit lines of the plurality of complementary bit lines.
2. 2. The memory device of claim 1, wherein: The first memory cell array is located on the first substrate, and The first bit line sense amplifier array is located on a second substrate that is located above the first substrate.
3. 3. The memory device of claim 2, wherein the second array of memory cells is located on the first substrate.
4. 4. The memory device of claim 1, the memory device further comprising: A second bit line sense amplifier array at least partially overlapping the second memory cell array along the vertical direction, wherein the second bit line sense amplifier array comprises: A plurality of second bit line sense amplifiers connected to (i) a plurality of second bit lines of the plurality of bit lines that are different from the plurality of first bit lines and (ii) a plurality of second complementary bit lines of the plurality of complementary bit lines that are different from the plurality of first complementary bit lines.
5. 5. The memory device of claim 4, wherein the second bit line sense amplifier array is on the same substrate as the first bit line sense amplifier array.
6. 6. The memory device of claim 4, Wherein the plurality of first bit lines are connected to a plurality of first cell wirings, wherein the plurality of first cell wirings are connected to the plurality of first bit line sense amplifiers through a plurality of first bonding contacts located in a first edge region of the first memory cell array, wherein the first edge region is not adjacent to the second memory cell array, and Wherein the plurality of second bit lines are connected to a plurality of second cell wirings, wherein the plurality of second cell wirings are connected to the plurality of second bit line sense amplifiers through a plurality of second bonding contacts located in a second edge region of the first memory cell array, wherein the second edge region is adjacent to the second memory cell array.
7. 7. The memory device of claim 6, Wherein the plurality of first complementary bit lines are connected to a plurality of third cell wirings, wherein the plurality of third cell wirings are connected to the plurality of first bit line sense amplifiers through a plurality of third bonding contacts located in a third edge region of the second memory cell array, wherein the third edge region is adjacent to the first memory cell array, and Wherein the plurality of second complementary bit lines are connected to a plurality of fourth cell wirings, wherein the plurality of fourth cell wirings are connected to the plurality of second bit line sense amplifiers through a plurality of fourth bonding contacts located in a fourth edge region of the second memory cell array, wherein the fourth edge region is not adjacent to the first memory cell array.
8. 8. The memory device of claim 7, wherein: the plurality of bit lines and the plurality of complementary bit lines extend in the first lateral direction, and The plurality of first unit wirings, the plurality of second unit wirings, the plurality of third unit wirings, and the plurality of fourth unit wirings extend in the first lateral direction.
9. 9. The memory device of claim 8, further comprising a cell routing layer on the first memory cell array and the second memory cell array, Wherein the plurality of first unit wirings, the plurality of second unit wirings, the plurality of third unit wirings, and the plurality of fourth unit wirings are located in the unit wiring layer.
10. 10. The memory device of claim 4, wherein: the plurality of first bit lines and the plurality of second bit lines are alternately arranged along a second lateral direction intersecting the first lateral direction, and The plurality of first complementary bit lines and the plurality of second complementary bit lines are alternately arranged along the second lateral direction.
11. 11. The memory device of claim 4, wherein: two first bit line sense amplifiers of the plurality of first bit line sense amplifiers are connected to two adjacent first bit lines of the plurality of first bit lines, One of the plurality of second bit lines is arranged between the two adjacent first bit lines, and Wherein the two first bit line sense amplifiers are spaced apart in the first lateral direction.
12. 12. The memory device of claim 4, Wherein the plurality of first bit lines are connected to a plurality of first cell wirings, wherein the plurality of first cell wirings are connected to the plurality of first bit line sense amplifiers through a plurality of first bonding contacts located in a first edge region of the first memory cell array, wherein the first edge region is not adjacent to the second memory cell array, and Wherein the plurality of second bit lines are connected to a plurality of second cell wirings, wherein the plurality of second cell wirings are connected to the plurality of second bit line sense amplifiers through a plurality of second bonding contacts located in the first edge region.
13. 13. The memory device of claim 12, Wherein the plurality of first complementary bit lines are connected to a plurality of third cell wirings, wherein the plurality of third cell wirings are connected to the plurality of first bit line sense amplifiers through a plurality of third bonding contacts located in a second edge region of the second memory cell array, wherein the second edge region is not adjacent to the first memory cell array, and Wherein the plurality of second complementary bit lines are connected to a plurality of fourth cell wirings, wherein the plurality of fourth cell wirings are connected to the plurality of second bit line sense amplifiers through a plurality of fourth bonding contacts located in the second edge region.
14. 14. The memory device of claim 13, wherein: Two adjacent first bit lines of the plurality of first bit lines and two adjacent second bit lines of the plurality of second bit lines are alternately arranged along a second lateral direction intersecting the first lateral direction, and Two adjacent ones of the plurality of first complementary bit lines and two adjacent ones of the plurality of second complementary bit lines are alternately arranged along the second lateral direction.
15. 15. The memory device of claim 14, wherein: Two first bit line sense amplifiers of the plurality of first bit line sense amplifiers are connected to the two adjacent first bit lines, an Wherein the two first bit line sense amplifiers are spaced apart in the first lateral direction.
16. 16. A memory device, the memory device comprising: A first substrate including a first block including a plurality of first memory cells and a plurality of bit lines connected to the plurality of first memory cells, and a second block including a plurality of second memory cells and a plurality of complementary bit lines connected to the plurality of second memory cells, and A second substrate over the first substrate, wherein the second substrate includes a bit line sense amplifier, Wherein the bit line sense amplifier at least partially overlaps the first block in a vertical direction, Wherein the bit line sense amplifier is connected to (i) a first bit line of the plurality of bit lines and (ii) a first complementary bit line of the plurality of complementary bit lines, and wherein the first complementary bit line corresponds to the first bit line.
17. 17. The memory device of claim 16, wherein: the plurality of bit lines are located on the plurality of first memory cells, the plurality of complementary bit lines are located on the plurality of second memory cells, and The first substrate includes a unit wiring layer including: A first cell wiring connecting the first bit line and the bit line sense amplifier, an And a second cell wiring connecting the first complementary bit line and the bit line sense amplifier.
18. 18. The memory device of claim 17, wherein: The first unit wiring overlaps the first block in the vertical direction, and The second unit wirings overlap the first and second blocks along the vertical direction.
19. 19. The memory device according to claim 17, wherein the second substrate includes a plurality of through vias connecting the first cell wiring and the second cell wiring to the bit line sense amplifier.
20. 20. A memory device, the memory device comprising: A first memory cell array including a plurality of bit lines; a second memory cell array comprising a plurality of complementary bit lines, wherein the second memory cell array is adjacent to the first memory cell array in a first direction; A first bit line sense amplifier array located on and at least partially overlapping the first memory cell array in a vertical direction, wherein the first bit line sense amplifier array is connected to (i) a first plurality of bit lines and (ii) a first plurality of complementary bit lines of the plurality of bit lines, and A second bit line sense amplifier array located on and at least partially overlapping the second memory cell array along the vertical direction, wherein the second bit line sense amplifier array is connected to (i) a second plurality of bit lines of the plurality of bit lines that are different from the first plurality of bit lines and (ii) a second plurality of complementary bit lines of the plurality of complementary bit lines that are different from the first plurality of complementary bit lines.

Description

Memory device Technical Field The present disclosure relates to memory devices. Background Volatile memory devices, such as Dynamic Random Access Memory (DRAM), store data by storing charge in a capacitive load (capacitor) of a memory cell and read data by determining the charge stored in the capacitor. The bit line sense amplifier may be connected to the memory cell to sense data stored in the memory cell. The bit line sense amplifier may detect and amplify a voltage difference between a bit line and a complementary bit line determined according to data stored in the memory cell. Meanwhile, when designing a DRAM by employing an open bit line structure, a dummy bit line is required for sensing the outermost memory cell array block, which may become a factor that deteriorates integration or manufacturing efficiency of the semiconductor memory device, such as the total number of die per wafer (gross DIE PER WAFER) or the net number of die per wafer (NET DIE PER WAFER). Disclosure of Invention Some aspects of the present disclosure relate to memory devices that may provide a higher total die per wafer and/or other advantages as discussed herein. A memory device according to some implementations of the present disclosure may include a first memory cell array including a plurality of bit lines, a second memory cell array including a plurality of complementary bit lines corresponding to the plurality of bit lines and disposed adjacent to the first memory cell array in a first direction, and a first bit line sense amplifier array having at least a portion overlapping the first memory cell array on the first memory cell array and including a plurality of first bit line sense amplifiers connected to a plurality of first bit lines among the plurality of bit lines and a plurality of first complementary bit lines among the plurality of complementary bit lines. A memory device according to some implementations of the present disclosure may include a first substrate including a first chunk including a plurality of first memory cells and a plurality of bit lines connected to the plurality of first memory cells, and a second chunk including a plurality of second memory cells and a plurality of complementary bit lines connected to the plurality of second memory cells, and a second substrate over the first substrate and including a bit line sense amplifier connected to one of the plurality of bit lines and one of the plurality of complementary bit lines and disposed on the first chunk, the one complementary bit line corresponding to one of the plurality of bit lines. A memory device according to some implementations of the present disclosure may include a first memory cell array including a plurality of bit lines, a second memory cell array including a plurality of complementary bit lines and disposed adjacent to the first memory cell array in a first direction, a first bit line sense amplifier array disposed on the first memory cell array and connected to a first plurality of bit lines among the plurality of bit lines and a first plurality of complementary bit lines among the plurality of complementary bit lines, and a second bit line sense amplifier array disposed on the second memory cell array and connected to a second plurality of bit lines among the plurality of bit lines and different from the first plurality of complementary bit lines. Drawings Fig. 1 is a block diagram showing an example of a memory device. Fig. 2 is a perspective diagrammatic view showing an example of a memory device. Fig. 3 is a diagram showing an example of the memory device shown in fig. 2. Fig. 4 is a perspective diagrammatic view showing an example of a memory device. Fig. 5 is a diagram showing an example of the memory device shown in fig. 4. Fig. 6 is a diagram showing an example of a memory device. Fig. 7 is a diagram showing an example of a memory cell array included in the memory device. Fig. 8 is a circuit diagram showing an example of a bit line sense amplifier included in a memory device. Fig. 9 is a diagram showing an example of a memory device. Fig. 10 is a diagram showing an example of a memory device. Fig. 11 is a diagram showing an example of a memory device. Fig. 12 is a diagram showing an example of a memory device. Fig. 13 is a perspective diagrammatic view showing an example of a memory device. Fig. 14 is a cross-sectional view of an example of a memory device. Fig. 15 is a cross-sectional view of an example of a memory device. Fig. 16 is a block diagram illustrating an example of a computing device. Detailed Description In the following detailed description, certain examples are described by way of illustration. As those skilled in the art will recognize, the described examples may be modified in various different ways, all without departing from the spirit or scope of the present disclosure. Like reference numerals designate like elements throughout the specification. In the flowcharts described with reference to the drawin