CN-121999832-A - Memory device and memory system

Abstract

The invention provides a memory device and a memory system. The memory device includes a memory string. The memory string includes first and second string portions. The first string portion stores stored filter bits and compares the input filter bits to the stored filter bits. The second string portion stores the stored calculation bits and compares the input calculation bits with the stored calculation bits, wherein the string current signal has a first current level when the input filter bits are different from the stored filter bits. When the input filter bit is equal to the stored filter bit and the input calculation bit and the stored calculation bit have a first difference, the string current signal has a second current level. When the input filter bit is equal to the stored filter bit and the input calculation bit and the stored calculation bit have a second difference, the string current signal has a third current level.

Inventors

• ZENG BAIHAO

Assignees

• 旺宏电子股份有限公司

Dates

Publication Date

20260508

Application Date

20250324

Priority Date

20250312

Claims (20)

1. 1. A memory device comprising a memory string for generating a string current signal, the memory string comprising: a first string portion (T9-T12) for storing at least one stored filter bit and comparing at least one input filter bit with the at least one stored filter bit, and A second string portion (T1-T8) coupled in series with the first string portion and configured to store a plurality of stored computation bits and compare a plurality of input computation bits with the stored computation bits, Wherein the string current signal has a first current level (IL 0) when an input value 1 of the at least one input filtered bit is different from a stored value 2 of the at least one stored filtered bit, When the input value of the at least one input filter bit is equal to the stored value of the at least one stored filter bit and an input value 1 of the input calculation bits and a stored value 1 of the stored calculation bits have a first difference of 0, the string current signal has a second current level (IL 1), and When the input value of the at least one input filter bit is equal to the stored value of the at least one stored filter bit and the input value 1 of the input calculation bits and the stored value 2 of the stored calculation bits have a second difference value 1, the string current signal has a third current level (IL 2).
2. 2. The memory device of claim 1, wherein each of the second current level and the third current level is greater than the first current level, and The second current level and the third current level are different from each other.
3. 3. The memory device of claim 2, wherein the first difference is less than the second difference, and The second current level is greater than the third current level.
4. 4. The memory device of claim 2, wherein the string current signal has a fourth current level (IL 3) when the input value of the at least one input filtered bit is equal to the stored value of the at least one stored filtered bit and the input value 1 of the input calculated bits and the stored value 2 of the stored calculated bits have a third difference value 2, The third difference is greater than each of the first difference and the second difference, and The fourth current level is less than each of the second current level and the third current level.
5. 5. The memory device of claim 4, wherein the string current signal has a fifth current level (IL 4) when the input value of the at least one input filtered bit is equal to the stored value of the at least one stored filtered bit and the input value 1 of the input calculated bits and the stored value 4 of the stored calculated bits have a fourth difference value 3, The fourth difference is greater than the third difference, and The fifth current level is less than the fourth current level and greater than the first current level.
6. 6. The memory device of claim 1, wherein the first string portion comprises a plurality of switching elements, When the stored value of the at least one stored filter bit has a range of 0-2, each of the switching elements has a first threshold voltage Level (LVT).
7. 7. The memory device of claim 6, wherein When the stored value of the at least one stored filter bit has the range and the at least one input filter bit has a first input value of 1, each of the switching elements is turned on, and When the stored value of the at least one stored filter bit has the range and the at least one input filter bit has a second input value 2 different from the first input value, each of the switching elements is turned on.
8. 8. The memory device of claim 6, wherein the switching elements are configured to receive a plurality of word line signals, When the input value of the at least one input filter bit has the range, each of the word line signals has a first voltage level (VH), and each of the switching elements is turned on.
9. 9. A memory device comprising a memory string for generating a string current signal, the memory string comprising: A first string part including a plurality of first switching elements (T9-T12) for storing at least one storage filter bit, and A second string part including a plurality of second switching elements (T1-T8) coupled in series with the first switching elements and storing a plurality of storage calculation bits, Wherein the first switch elements are respectively used for receiving a plurality of first word line signals (WL 9-WL 12) carrying at least one input filtering bit, The second switch elements are respectively used for receiving a plurality of second word line signals (WL 1-WL 8) carrying a plurality of input computing bits, When an input value 1 of the at least one input filter bit is different from a stored value 2 of the at least one stored filter bit, at least one of the first switching elements is turned off, When the input value of the at least one input filter bit is equal to the stored value of the at least one stored filter bit and an input value 1 of the input calculation bits and a stored value 1 of the stored calculation bits have a first difference of 0, the string current signal has a first current level (IL 1), and When the input value of the at least one input filter bit is equal to the stored value of the at least one stored filter bit and the input value 1 of the input calculation bits and the stored value 2 of the stored calculation bits have a second difference value 1, the string current signal has a second current level (IL 2).
10. 10. The memory device of claim 9, wherein each of the first switching elements is turned on when the input value of the at least one input filter bit is equal to the stored value of the at least one stored filter bit.
11. 11. The memory device of claim 9, wherein the first difference is less than the second difference, and The first current level is greater than the second current level.
12. 12. The memory device of claim 9, wherein the second switching elements comprise: A third switching element (T4) for having a first threshold voltage Level (LVT) when the stored calculation bits have a first stored value 1 and for having a second threshold voltage level (HVT) greater than the first threshold voltage level when the stored calculation bits have a second stored value 2.
13. 13. The memory device of claim 12, wherein the second switching elements further comprise: A fourth switching element (T6) for having the first threshold voltage level when the stored bits have the second stored value and for having the second threshold voltage level when the stored bits have a third stored value 3, Wherein the third stored value is greater than each of the second stored value and the first stored value.
14. 14. The memory device of claim 13, wherein the second switching elements further comprise: A fifth switching element (T8) for having the first threshold voltage level when the stored calculation bits have the third stored value and for having the second threshold voltage level when the stored calculation bits have a fourth stored value 4, Wherein the fourth stored value is greater than the third stored value.
15. 15. The memory device of claim 13, wherein the second switching elements further comprise: a fifth switching element (T3) for having the second threshold voltage level when the stored calculation bits have the first stored value, for having the first threshold voltage level when the stored calculation bits have the second stored value, and for having the first threshold voltage level when the stored calculation bits have the third stored value.
16. 16. The memory device of claim 15, wherein the second switching elements further comprise: A sixth switching element (T5) for having the second threshold voltage level when the stored calculation bits have the first stored value, for having the second threshold voltage level when the stored calculation bits have the second stored value, and for having the first threshold voltage level when the stored calculation bits have the third stored value.
17. 17. A memory system comprising a plurality of memory strings for generating a plurality of bit line signals, the memory strings comprising: A plurality of first memory word strings (MS1_1-MS1_K) for comparing a plurality of first stored data and a plurality of input data (IDT 1-IDTK) to generate a plurality of first word string current signals (IS 1_1-IS1_K) and adding the first word string current signals to generate a first bit line signal (BL 1), and A plurality of second memory word strings (MS2_1-MS2_K) for comparing a plurality of second stored data and the input data to generate a plurality of second word string current signals (IS 2_1-IS2_K), and adding the second word string current signals to generate a second bit line signal (BL 2), Wherein in response to a third memory string (MS 1-1) of the first memory strings storing a stored value of the stored filter bits different from an input value of the input filter bits of a first input data (IDT 1) of the input data, at least one switching element of the third memory string is turned off, and In response to a stored value of a stored filter bit stored in a fourth memory string (MS2_1) of the second memory strings being equal to the input value of the input filter bits of the first input data, a third string current signal (IS 2_1) generated by the fourth memory string increases in current level as a difference between a stored value of the stored calculation bit stored in the fourth memory string and an input value of the input calculation bit of the first input data decreases.
18. 18. The memory system of claim 17, wherein in response to a stored value of the stored filter bits stored in a fifth one of the first memory strings (MS 1 2) being different from an input value of the input filter bits of a second one of the input data (IDT 2), at least one switching element in the fifth memory string is turned off.
19. 19. The memory system of claim 18, wherein a fourth string current signal (is2_2) generated by a sixth memory string (MS 2_2) in response to the stored value of the stored filter bits stored by the sixth memory string being equal to the input value of the input filter bits of the second input data, IS greater as a difference between a stored value of the stored calculation bits stored by the sixth memory string and an input value of the input calculation bits of the second input data IS smaller.
20. 20. The memory system of claim 19, wherein the third string current signal has a first current level (IL 4) in response to a first difference 3 between the stored value 4 of the stored bits of the fourth memory string and the input value 1 of the input bits of the first input data, In response to a second difference 2 between the stored value 3 of the stored bits of the sixth memory word and the input value 1 of the input bits of the second input data, the fourth word current signal has a second current level (IL 3), The first difference is greater than the second difference, and the first current level is less than the second current level.

Description

Memory device and memory system Technical Field The present invention relates to a memory technology, and more particularly, to a memory device and a memory system. Background Existing in-memory search functions may compare input data to stored data to perform a matching operation. However, the chip power consumed by existing in-memory search functions is high. Therefore, how to design a memory device that saves chip power and can perform an in-memory search function is an important topic in the art. Disclosure of Invention Embodiments of the present invention include a memory device. The memory device includes a memory word string for generating a word string current signal. The memory string includes a first string portion and a second string portion. The first string portion is used for storing at least one stored filter bit and comparing at least one input filter bit with at least one stored filter bit. The second string portion is coupled in series with the first string portion and configured to store a plurality of storage calculation bits and compare the plurality of input calculation bits with the storage calculation bits, wherein the string current signal has a first current level when an input value of at least one input filter bit is different from a storage value of at least one storage filter bit, the string current signal has a second current level when the input value of at least one input filter bit is equal to the storage value of at least one storage filter bit and an input value of the input calculation bit and a storage value of the storage calculation bit have a first difference, and the string current signal has a third current level when the input value of at least one input filter bit is equal to the storage value of at least one storage filter bit and the input value of the input calculation bit and the storage value of the storage calculation bit have a second difference. In some embodiments, each of the second current level and the third current level is greater than the first current level, and the second current level and the third current level are different from each other. In some embodiments, the first difference is less than the second difference and the second current level is greater than the third current level. In some embodiments, when the input value of the at least one input filtered bit is equal to the stored value of the at least one stored filtered bit and the input value of the input calculated bit and the stored value of the stored calculated bit have a third difference, the string current signal has a fourth current level, the third difference is greater than each of the first difference and the second difference, and the fourth current level is less than each of the second current level and the third current level. In some embodiments, when the input value of the at least one input filtered bit is equal to the stored value of the at least one stored filtered bit and the input value of the input calculated bit and the stored value of the stored calculated bit have a fourth difference, the string current signal has a fifth current level, the fourth difference is greater than the third difference, and the fifth current level is less than the fourth current level and greater than the first current level. In some embodiments, the first string portion includes a plurality of switching elements, each of the switching elements having a first threshold voltage level when the stored value of the at least one stored filter bit has a range. In some embodiments, each of the switching elements is turned on when the stored value of the at least one stored filter bit has a range and the at least one input filter bit has a first input value, and each of the switching elements is turned on when the stored value of the at least one stored filter bit has a range and the at least one input filter bit has a second input value different from the first input value. In some embodiments, the switching elements are respectively configured to receive a plurality of word line signals, each of the word line signals having a first voltage level when the input value of the at least one input filter bit has a range, and each of the switching elements being turned on. Embodiments of the present invention include a memory device. The memory device includes a memory word string for generating a word string current signal. The memory string includes a first string portion and a second string portion. The first string portion includes a plurality of first switching elements and is used for storing at least one stored filter bit. A second string portion includes a plurality of second switching elements coupled in series with the first switching elements and is configured to store a plurality of stored computation bits. The first switch element is used for receiving a plurality of first word line signals carrying at least one input filtering bit, the second switch element is used for receiving a plu