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CN-121999833-A - High-density 4T1C eDRAM macro structure for low-temperature true three-value logic memory internal calculation

CN121999833ACN 121999833 ACN121999833 ACN 121999833ACN-121999833-A

Abstract

The invention relates to a high-density 4T1C eDRAM macro structure for low-temperature true three-value logic memory, belonging to the technical field of memory and computing architecture integration, comprising a reference voltage generation module, a logic circuit and a logic circuit, wherein the reference voltage generation module provides two key reference levels required by three-value judgment; the system comprises a row decoder for selecting a target storage unit, a low-temperature three-value write driving module for transmitting three-value voltage to the selected storage unit, a low-temperature three-value storage array, a read/calculate decoder for reading/calculating the level state of a word line, a three-value sense amplifier for completing three-value voltage comparison, an output processing circuit connected with the output end of the three-value sense amplifier, and a control module for coordinating the working time sequence of each module, wherein the 4T1C three-value storage unit realizes single-unit storage of true three-value data through three stable voltage states of a storage node. The invention realizes high-density true three-value data storage and multiple true three-value logic operation under the low-temperature condition.

Inventors

  • HA YAJUN
  • NING BIN

Assignees

  • 上海科技大学

Dates

Publication Date
20260508
Application Date
20260109

Claims (10)

  1. 1. A high density 4t1c eDRAM macrostructure for low temperature true three value logic memory calculations, comprising: The reference voltage generation module is used for providing two key reference levels required by three-value judgment through a global reference voltage line; A row decoder for generating two sets of complementary row control signals to select the target memory cell; the low-temperature three-value write driving module is used for transmitting the coded three-value voltage to the selected unit; The low-temperature three-value storage array is an array structure formed by a plurality of 4T1C three-value storage units; A read/calculate decoder for dynamically configuring a level state of the read/calculate word line according to the operation mode; the three-value sense amplifier is used for completing three-value voltage comparison through a two-step sampling judgment mechanism; the output processing circuit is connected with the output end of the three-value sensitive amplifier; The control module is used for coordinating the working time sequence of each module; The 4T1C three-value storage unit adopts a compact framework of four transistors and one capacitor, and realizes that a single unit stores true three-value data through three stable voltage states of a storage node.
  2. 2. The high-density 4T1C eDRAM macrostructure for low-temperature true three-valued logic memory computation of claim 1, wherein the 4T1C three-valued memory cell comprises: the first transistor and the second transistor form complementary transmission gates, the gates of the complementary transmission gates are respectively controlled by complementary row control signals, and accurate regulation and control of the conduction state between the writing bit line and the storage node are realized; The third transistor and the fourth transistor are used as two independent read access transistors, the grid electrodes of the third transistor and the fourth transistor are directly connected to the storage node, and the source-drain paths are respectively connected into a positive read bit line and a negative read bit line to form a decoupled double-read-path architecture; and a metal-oxide-metal capacitor integrated at the storage node for increasing the node capacitance.
  3. 3. The high-density 4t1c eDRAM macro structure for low temperature true three value logic memory as recited in claim 2, wherein the complementary pass gate is comprised of a PMOS transistor having a gate connected to the first row control signal and an NMOS transistor having a gate connected to the second row control signal complementary to the first row control signal, the drains of the PMOS transistor and the NMOS transistor being commonly connected to the write bit line and the sources being commonly connected to the storage node.
  4. 4. The high-density 4t1c eDRAM macrostructure for low-temperature true three-valued logic memory computation of claim 2, wherein the dual read path architecture comprises: the positive read bit line is connected with the source electrode of the third transistor, and the negative read bit line is connected with the drain electrode of the fourth transistor; During read operation, the positive read bit line and the negative read bit line work independently; During the logic calculation operation in the memory, the positive reading bit line and the negative reading bit line are in short circuit through the transmission gate to form a common reading bit line.
  5. 5. The high-density 4t1c eDRAM macrostructure for low-temperature true three-valued logic memory computation of claim 1, wherein the low-temperature three-valued write driver module comprises: a write enable switching transistor, the timing window being controlled by a complementary write enable signal; A first series path formed of two PMOS transistors for driving the write bit line high in response to the first input code; a second series path formed of two NMOS transistors for driving the write bit line to a low level in response to a second input code; and a self-biasing inverter circuit that stabilizes the write bit line to an intermediate level through a threshold voltage boosting and shorting inverter mechanism in response to a third input code.
  6. 6. The high-density 4t1c eDRAM macro structure for low temperature true three value logic memory computation of claim 5 wherein the self biasing inverter circuit comprises: an NMOS transistor having a gate connected to an input signal and a source connected to a drain of one of the PMOS transistors; a PMOS transistor having a gate connected to a low-level signal and a source connected to a power supply voltage; And a short-circuit inverter composed of a PMOS transistor and an NMOS transistor, the input terminal and the output terminal of which are short-circuited and connected to the write bit line; When the input code is [11] or [00], the PMOS transistor raises the source of the NMOS transistor by about a threshold voltage, stabilizing the short-circuited inverter self-bias to an intermediate level.
  7. 7. The high-density 4T1C eDRAM macro structure for low-temperature true three-value logic memory computation of claim 1, wherein the reference voltage generation module employs a reference voltage generation cell array similar to the 4T1C three-value memory cell structure, and generates two reference levels in two steps of operation through a charge sharing mechanism: the first step, the first control signal is set low, the second control signal is set high, the storage nodes of the selected group are charged to a high level, and the storage nodes of the unselected group are discharged to a low level; And secondly, setting the first control signal high and the second control signal low, starting the transmission gate to short the selected group of storage nodes to redistribute charges, and finally forming stable reference voltage on the reference voltage line.
  8. 8. The high-density 4t1c eDRAM macro structure for low temperature true three value logic memory computation of claim 1, wherein the three value sense amplifier comprises: A precharge control transistor for controlling a precharge operation by a precharge signal; The transmission gate group is used for sampling the positive reading bit line, the negative reading bit line data signal and the reference voltage signal and isolating the input end and the output end of the amplifier in the sampling stage; the latch circuit is used for comparing the voltage and latching the result; and an in-memory computation-dedicated transfer gate activated only when performing a ternary logic operation to short the positive and negative read bit lines; The three-value sensitive amplifier outputs a high-order result signal by comparing the first step with a first reference level and outputs a low-order result signal by comparing the second step with a second reference level through a two-step sampling judgment flow, and the two steps of results are combined to form complete three-value output.
  9. 9. The high-density 4T1C eDRAM macro structure for low-temperature true three-value logic memory according to claim 8, wherein the three-value sense amplifier supports a unified true three-value logic memory computing mechanism, positive and negative read word lines of different memory cells in the same column are dynamically configured through a read/compute decoder, and the multi-stage voltage comparison and result encoding are completed in two steps of time sequences by matching with a reference voltage generating module and the three-value sense amplifier, so that the double-operand three-value logic operation of a first operand and a second operand is realized.
  10. 10. The high-density 4t1c eDRAM macro structure for low-temperature true tri-value in-memory computing of claim 9, wherein the true tri-value in-memory computing mechanism supports MIN, MAX, CONS, ANY binary operations and STI, NTI unigram operations, all operations follow a completely consistent two-step execution framework: In the first step, according to the connection relation between the NMOS path or PMOS path and the high level or low level configured by the operation type, the three-value sense amplifier samples the common read bit line voltage and compares the common read bit line voltage with the first reference level to output a high-order result; In the second step, the path configuration is adjusted and the three-value sense amplifier resamples the common read bit line voltage and compares it with the second reference level to output a low-order result.

Description

High-density 4T1C eDRAM macro structure for low-temperature true three-value logic memory internal calculation Technical Field The invention belongs to the technical field of integration of a memory and a computing architecture, and particularly relates to a true three-value logic memory internal computing embedded dynamic random access memory (eDRAM) macro structure working in a low-temperature environment. Background With the development of data-intensive applications such as artificial intelligence and quantum computing, the traditional 'memory-computing-separation' architecture faces the problems of high data moving overhead, high energy consumption and prominent bandwidth bottleneck. Logic in-memory computing has become one of the important directions of efficient computing systems by directly performing some of the logic operations within the memory array, effectively reducing data movement between memory operations. In a multi-valued logic system (radix > 2), three-valued logic (radix=3) can achieve data size compression of up to 36.9% under the constraint of equal symbol error rate, while having circuit complexity and memory density advantages, and is therefore considered one of the most engineering viable multi-valued logic forms. On the other hand, the low-temperature operation can obviously reduce thermal noise and leakage current and improve the stability of the threshold voltage of the device and the signal margin. For the memory structure based on capacitance storage charge of the eDRAM, the low temperature can greatly prolong the data retention time and reduce the refreshing cost, so that the memory structure has more outstanding density and energy efficiency advantages than normal temperature in a low temperature environment. The prior art mainly has the following defects: 1. the true three-value storage unit structure is limited in that the conventional embedded DRAM is usually optimized for normal-temperature two-value storage, and when the conventional embedded DRAM tries to expand to three-value or multi-value storage, a multi-unit joint coding mode is usually adopted, so that the storage density is reduced; 2. The existing three-value logic related work, the three-value operation is realized based on a CMOS three-value logic gate, a carbon nanotube device or a memristor array, and the multi-level logic can be realized, but the dependence on the process and the peripheral is strong, and the large-scale integration under the mainstream CMOS process is difficult; 3. The multi-value memory calculation is still 'binary coding calculation', wherein the existing scheme of combining multiple-value memory calculation only utilizes multiple levels on a memory side to improve the memory density, and binary coding is still adopted on a calculation side to perform operation. The multi-level unit is used for improving the storage throughput, but the multi-value is required to be decoded into multi-bit binary operation by the calculation operation, the Boolean operation is only realized by the logic in-memory operation, and the advantages of the three-value logic in the aspects of arithmetic and logic expression are not fully utilized. Such schemes, while increasing density, do not fully release the energy efficiency and area potential of the three-value calculation. Therefore, a high-density true three-value eDRAM macro structure which is realized under a mainstream CMOS process and faces to a low-temperature environment is needed, and the macro structure can store three-value data by a single unit, has long retention time and reliable read-write capability at a low temperature, and supports a set of complete and energy-efficient true three-value logic in-memory computing operation. Disclosure of Invention The invention is developed around three problems existing in the existing low-temperature three-value logic memory computing system, namely, three-value data is usually realized through multi-unit coding, so that storage density is insufficient, real three-value writing and reading depend on complex peripheral equipment and an analog comparison circuit, stable work is difficult to realize in a large-scale array, a unified architecture is not formed by multi-value storage and logic memory computing, and most schemes are multi-value only on a storage side and still are two-value coding on a computing side. In order to solve the above problems, the technical solution of the present invention provides a high-density 4t1c eDRAM macrostructure for low-temperature true three-value logic memory computation, comprising: The reference voltage generation module is used for providing two key reference levels required by three-value judgment through a global reference voltage line; A row decoder for generating two sets of complementary row control signals to select the target memory cell; the low-temperature three-value write driving module is used for transmitting the coded three-value voltage to the selected