CN-121999834-A - Static memory and manufacturing method thereof

Abstract

The application provides a static memory and a manufacturing method thereof, wherein the static memory comprises a first inverter, a first control transistor and a second control transistor, the input end of the first inverter is used as a storage node, the first control transistor and the second control transistor are arranged in a first active area and along a second direction, the first inverter is arranged in a third active area, and the first active area and the third active area are arranged along the first direction, so that the read-write path length from the first control transistor to the storage node is consistent with the read-write path length from the second control transistor to the storage node, and the read-write path length from the first port is consistent with the read-write path length from the second port, thereby solving the problem of read-write failure caused by inconsistent read-write paths.

Inventors

• WU HUAFENG

Assignees

• 上海光通信有限公司

Dates

Publication Date

20260508

Application Date

20241106

Claims (10)

1. 1. A static memory, the static memory comprising: the first inverter, the first control transistor and the second control transistor, wherein the input end of the first inverter is used as a storage node; A first pole of the first control transistor is connected with a first port bit line, a second pole of the first control transistor is connected with the storage node, a first pole of the second control transistor is connected with a second port bit line, and a second pole of the second control transistor is connected with the storage node; The first control transistor and the second control transistor are located in a first active region and are arranged along a second direction, the first inverter is located in a third active region, and the first active region and the third active region are arranged along a first direction perpendicular to the second direction; the read-write path length from the first control transistor to the storage node is consistent with the read-write path length from the second control transistor to the storage node.
2. 2. The static memory of claim 1, wherein the first inverter comprises a first pull-down transistor and a third pull-down transistor; A first pole of the first pull-down transistor and a first pole of the third pull-down transistor are connected to each other as an input terminal of the first inverter; the first pull-down transistor and the third pull-down transistor are located in the third active region and arranged along the second direction.
3. 3. The static memory of claim 2, wherein the first inverter comprises a first pull-up transistor, the first pull-up transistor being located in the second active region; the first active region, the second active region and the third active region are sequentially arranged along a first direction.
4. 4. A static memory according to claim 3, characterized in that it comprises: a second inverter, a third control transistor, and a fourth control transistor; the second inverter includes a second pull-down transistor and a fourth pull-down transistor; The first pole of the second pull-down transistor and the first pole of the fourth pull-down transistor are connected to each other as complementary storage nodes; The complementary read path length of the third control transistor to the complementary storage node is consistent with the complementary read path length of the fourth control transistor to the complementary storage node.
5. 5. The static memory of claim 4, wherein the second pull-down transistor and the fourth pull-down transistor are located in a fourth active region and arranged along the second direction; The third control transistor and the fourth control transistor are located in a sixth active region and arranged along the second direction; the fourth active region and the sixth active region are arranged along a first direction.
6. 6. The static memory of claim 5, wherein the second inverter comprises a second pull-up transistor, the second pull-up transistor being located in a fifth active region; The fourth active region, the fifth active region and the sixth active region are sequentially arranged along a first direction.
7. 7. A method of manufacturing a static memory, characterized in that the method is used for the static memory of any one of claims 1-6, the method comprising: Forming a first active region and a third active region arranged along a first direction; forming the first control transistor and the second control transistor which are arranged along a second direction in the first active region, wherein the second direction and the first direction are two directions which are perpendicular to each other on a plane; And forming the first inverter in the third active region to control the read-write path length from the first control transistor to the storage node to be consistent with the read-write path length from the second control transistor to the storage node.
8. 8. The method of claim 7, wherein the first inverter comprises a first pull-down transistor and a third pull-down transistor, a first pole of the first pull-down transistor and a first pole of the third pull-down transistor being connected to each other; said forming in said third active region along said first inverter comprising: forming the first pull-down transistor and the third pull-down transistor arranged in the second direction in the third active region; and/or; the first inverter includes a first pull-up transistor; the forming of the first active region and the third active region arranged along the first direction includes: First, second and third active regions arranged in a first direction are formed, and the first pull-up transistor is formed in the second active region.
9. 9. The method of claim 7, wherein the static memory comprises a second inverter, a third control transistor, and a fourth control transistor, wherein the second inverter comprises a second pull-down transistor and a fourth pull-down transistor, wherein a first pole of the second pull-down transistor and a first pole of the fourth pull-down transistor are connected to each other as complementary storage nodes, and wherein the method further comprises: forming a fourth active region and a sixth active region arranged along the first direction; forming the second pull-down transistor and the fourth pull-down transistor arranged in the second direction in the fourth active region; Third and fourth control transistors are formed in the sixth active region and arranged in the second direction to control a complementary read path length of the third control transistor to the complementary storage node to coincide with a complementary read path length of the fourth control transistor to the complementary storage node.
10. 10. The method of claim 9, wherein the second inverter comprises a second pull-up transistor; the forming of the fourth active region and the sixth active region arranged along the first direction includes: forming a fourth active region, a fifth active region and a sixth active region arranged along the first direction; The method further comprises the steps of: the second pull-up transistor is formed in the fifth active region.

Description

Static memory and manufacturing method thereof Technical Field The present application relates to the field of memories, and more particularly, to a static memory and a method for manufacturing the same. Background The Dual-port static random access memory (Dual-Port Static Random Access Memory, DPSRAM) is a static memory with two independent access ports, and can perform read-write operation simultaneously, thereby improving the efficiency and the overall performance of the memory. How to reduce the read-write failure of static memory is a significant problem. Disclosure of Invention The application provides a static memory and a manufacturing method thereof, which solve the problem of read failure of the static memory. In a first aspect, the present application provides a static memory comprising: the first inverter, the first control transistor and the second control transistor, wherein the input end of the first inverter is used as a storage node; A first pole of the first control transistor is connected with a first port bit line, and a second pole of the first control transistor is connected with the storage node; a first pole of the second control transistor is connected with a second port bit line, and a second pole of the second control transistor is connected with the storage node; The first control transistor and the second control transistor are located in a first active area and are arranged along a second direction, and the first inverter is located in a third active area; the first active area and the third active area are arranged along a first direction, and the first direction and the second direction are two directions which are perpendicular to each other on a plane; the read-write path length from the first control transistor to the storage node is consistent with the read-write path length from the second control transistor to the storage node. The first inverter includes a first pull-down transistor and a third pull-down transistor; A first pole of the first pull-down transistor and a first pole of the third pull-down transistor are connected to each other as an input terminal of the first inverter; the first pull-down transistor and the third pull-down transistor are located in the third active region and arranged along the second direction. In some embodiments, the first inverter includes a first pull-up transistor, the first pull-up transistor being located in the second active region; the first active region, the second active region and the third active region are sequentially arranged along a first direction. In some embodiments, the static memory comprises: a second inverter, a third control transistor, and a fourth control transistor; the second inverter includes a second pull-down transistor and a fourth pull-down transistor; The first pole of the second pull-down transistor and the first pole of the fourth pull-down transistor are connected to each other as complementary storage nodes; The complementary read path length of the third control transistor to the complementary storage node is consistent with the complementary read path length of the fourth control transistor to the complementary storage node. In some embodiments, the second pull-down transistor and the fourth pull-down transistor are located in a fourth active region and arranged along the second direction; The third control transistor and the fourth control transistor are located in a sixth active region and arranged along the second direction; the fourth active region and the sixth active region are arranged along a first direction. In some embodiments, the second inverter includes a second pull-up transistor, the second pull-up transistor being located in a fifth active region; The fourth active region, the fifth active region and the sixth active region are sequentially arranged along a first direction. In a second aspect, the present application provides a method for manufacturing a static memory, the method being used for the static memory, the method comprising: Forming a first active region and a third active region arranged along a first direction; Forming the first inverters arranged along a second direction in the first active region, wherein the second direction and the first direction are two directions which are perpendicular to each other on a plane; And forming the first pull-down transistor and the third pull-down transistor which are arranged along the second direction in the third active region so as to control the read-write path length from the first control transistor to the storage node to be consistent with the read-write path length from the second control transistor to the storage node. In some embodiments, the first inverter includes a first pull-down transistor and a third pull-down transistor, a first pole of the first pull-down transistor and a first pole of the third pull-down transistor being connected to each other; said forming in said third active region along said first inverte