CN-121999835-A - Static memory and manufacturing method thereof

Abstract

The application provides a static memory and a manufacturing method thereof, wherein the static memory comprises a first inverter, a first control transistor and a second control transistor, the input end of the first inverter is used as a storage node, the first pole of the first control transistor is connected with a first port bit line, the second pole of the first control transistor is connected with the storage node, the first pole of the second control transistor is connected with a second port bit line, the second pole of the second control transistor is connected with the storage node, and the read-write path length from the first control transistor to the storage node is consistent with the read-write path length from the second control transistor to the storage node, so that the read-write path length from the first port is consistent with the read-write path length from the second port, and the read-write failure problem caused by inconsistent read-write path length is solved.

Inventors

• CAI QIAOMING
• WU HUAFENG

Assignees

• 上海光通信有限公司

Dates

Publication Date

20260508

Application Date

20241106

Claims (11)

1. 1. A static memory, the static memory comprising: A first inverter, a first control transistor, and a second control transistor; The input end of the first inverter is used as a storage node; A first pole of the first control transistor is connected with a first port bit line, and a second pole of the first control transistor is connected with the storage node; a first pole of the second control transistor is connected with a second port bit line, and a second pole of the second control transistor is connected with the storage node; the read-write path length from the first control transistor to the storage node is consistent with the read-write path length from the second control transistor to the storage node.
2. 2. The static memory of claim 1, wherein the first inverter comprises a first pull-down transistor and a third pull-down transistor; The first pole of the first pull-down transistor and the first pole of the third pull-down transistor are connected to each other as an input of the first inverter.
3. 3. The static memory of claim 2, wherein the first and second control transistors are located in a first active region and arranged in a second direction, and wherein the first and third control transistors are located in a second active region and arranged in the second direction; The first active region and the second active region are arranged along a first direction, and the second direction and the first direction are two directions which are perpendicular to each other on a plane.
4. 4. The static memory of claim 3, wherein the first inverter comprises a first pull-up transistor, a first pole of the pull-up transistor connecting a first pole of the first pull-down transistor and a first pole of the third pull-down transistor; The first pull-up transistor is positioned in the third active area; the first active region, the second active region and the third active region are sequentially arranged along the first direction.
5. 5. The static memory according to any one of claims 1-4, characterized in that it comprises: a second inverter, a third control transistor, and a fourth control transistor; the second inverter includes a second pull-down transistor and a fourth pull-down transistor; The first pole of the second pull-down transistor and the first pole of the fourth pull-down transistor are connected to each other as complementary storage nodes; The complementary read path length of the third control transistor to the complementary storage node is consistent with the complementary read path length of the fourth control transistor to the complementary storage node.
6. 6. The static memory of claim 5, wherein, The second pull-down transistor and the fourth control transistor are located in the fifth active region and arranged along the second direction; The third control transistor and the fourth pull-down transistor are located in a sixth active region and arranged along the second direction; The fifth active region and the sixth active region are arranged along a first direction, and the second direction and the first direction are two directions perpendicular to each other on a plane.
7. 7. The static memory of claim 6, wherein the second inverter comprises a second pull-up transistor, a first pole of the second pull-up transistor connecting a first pole of the second pull-down transistor and a first pole of the fourth pull-down transistor; the second pull-up transistor is positioned in the fourth active region; The fourth active region, the fifth active region and the sixth active region are sequentially arranged along a first direction.
8. 8. A method of manufacturing a static memory, characterized in that the method is used for the static memory of any one of claims 1-7, the method comprising: Forming a first inverter, a first control transistor and a second control transistor, wherein the input end of the first inverter is used as a storage node; Connecting a first pole and a second pole of the first control transistor with a first port bit line and the storage node respectively, and connecting a first pole and a second pole of the second control transistor with a second port bit line and the storage node respectively; and controlling the read-write path length from the first control transistor to the storage node to be consistent with the read-write path length from the second control transistor to the storage node.
9. 9. The method of claim 8, wherein the first inverter comprises a first pull-down transistor and a third pull-down transistor, a first pole of the first pull-down transistor and a first pole of the third pull-down transistor being connected to each other as an input of the first inverter; the controlling the read-write path length from the first control transistor to the storage node, consistent with the read-write path length from the second control transistor to the storage node, includes: Forming a first active region and a second active region arranged along a first direction; Forming the first pull-down transistor and the second control transistor arranged in a second direction in the first active region; Forming a first control transistor and the third pull-down transistor arranged along the second direction in the second active region so as to control the read-write path length from the first control transistor to the storage node to be consistent with the read-write path length from the second control transistor to the storage node; the first direction and the second direction are two directions perpendicular to each other on a plane.
10. 10. The method according to claim 9, wherein the method further comprises: Forming a second inverter, a third control transistor and a fourth control transistor, the input of the second inverter serving as a complementary storage node; connecting the first and second poles of the third control transistor with a first port complementary bit line and the complementary storage node, respectively, and connecting the first and second poles of the fourth control transistor with a second port complementary bit line and the complementary storage node, respectively; And controlling the complementary read path length of the third control transistor to the complementary storage node to be consistent with the complementary read path length of the fourth control transistor to the complementary storage node.
11. 11. The method of claim 10, wherein the second inverter comprises a second pull-down transistor and a fourth pull-down transistor, the first pole of the second pull-down transistor and the first pole of the fourth pull-down transistor being connected to each other as complementary storage nodes; The controlling the complementary read path length of the third control transistor to the complementary storage node, consistent with the complementary read path length of the fourth control transistor to the complementary storage node, comprises: forming a fifth active region and a sixth active region arranged along a first direction; forming the second pull-down transistor and the fourth control transistor arranged in a second direction in the fifth active region; The third control transistor and the fourth pull-down transistor are formed in the sixth active region to be arranged in the second direction so that a complementary read path length of the third control transistor to the complementary storage node is controlled to coincide with a complementary read path length of the fourth control transistor to the complementary storage node.

Description

Static memory and manufacturing method thereof Technical Field The present application relates to the field of memories, and more particularly, to a static memory and a method for manufacturing the same. Background The Dual-port static random access memory (Dual-Port Static Random Access Memory, DPSRAM) is a static memory with two independent access ports, and can perform read-write operation simultaneously, thereby improving the efficiency and the overall performance of the memory. How to reduce the read-write failure of static memory is a significant problem. Disclosure of Invention The application provides a static memory and a manufacturing method thereof, which solve the problem of read failure of the static memory. In a first aspect, the present application provides a static memory comprising: A first inverter, a first control transistor, and a second control transistor; The input end of the first inverter is used as a storage node; A first pole of the first control transistor is connected with a first port bit line, and a second pole of the first control transistor is connected with the storage node; a first pole of the second control transistor is connected with a second port bit line, and a second pole of the second control transistor is connected with the storage node; the read-write path length from the first control transistor to the storage node is consistent with the read-write path length from the second control transistor to the storage node. In some embodiments, the first inverter includes a first pull-down transistor and a third pull-down transistor; The first pole of the first pull-down transistor and the first pole of the third pull-down transistor are connected to each other as an input of the first inverter. In some embodiments, the first pull-down transistor and the second control transistor are located in a first active region and arranged in a second direction, and the first control transistor and the third pull-down transistor are located in a second active region and arranged in the second direction; The first active region and the second active region are arranged along a first direction, and the second direction and the first direction are two directions which are perpendicular to each other on a plane. In some embodiments, the first inverter comprises a first pull-up transistor having a first pole connected to a first pole of the first pull-down transistor and a first pole of the third pull-down transistor; The first pull-up transistor is positioned in the third active area; the first active region, the second active region and the third active region are sequentially arranged along the first direction. In some embodiments, the static memory comprises: a second inverter, a third control transistor, and a fourth control transistor; the second inverter includes a second pull-down transistor and a fourth pull-down transistor; The first pole of the second pull-down transistor and the first pole of the fourth pull-down transistor are connected to each other as complementary storage nodes; The complementary read path length of the third control transistor to the complementary storage node is consistent with the complementary read path length of the fourth control transistor to the complementary storage node. In some embodiments of the present invention, in some embodiments, The second pull-down transistor and the fourth control transistor are located in the fifth active region and arranged along the second direction; The third control transistor and the fourth pull-down transistor are located in a sixth active region and arranged along the second direction; The fifth active region and the sixth active region are arranged along a first direction, and the second direction and the first direction are two directions perpendicular to each other on a plane. In some embodiments, the second inverter includes a second pull-up transistor having a first pole connected to the first pole of the second pull-down transistor and the first pole of the fourth pull-down transistor; the second pull-up transistor is positioned in the fourth active region; The fourth active region, the fifth active region and the sixth active region are sequentially arranged along a first direction. In a second aspect, the present application provides a method for manufacturing a static memory, the method being used for the static memory, the method comprising: Forming a first inverter, a first control transistor and a second control transistor, wherein the input end of the first inverter is used as a storage node; Connecting a first pole and a second pole of the first control transistor with a first port bit line and the storage node respectively, and connecting a first pole and a second pole of the second control transistor with a second port bit line and the storage node respectively; and controlling the read-write path length from the first control transistor to the storage node to be consistent with the read-write pa