CN-121999837-A - Compensation current for PCM memory

Abstract

The present disclosure relates to compensation currents for PCM memories. The present disclosure relates to a memory block including rows and columns of phase change memory cells. The first MOS transistor couples a power supply voltage to an input terminal receiving a reference current, and has a gate connected to the input terminal. For each column, a second transistor couples the supply voltage to a corresponding output coupled to the column. A conductive rail connects the input terminal to the gate of the second transistor. The circuit selects the columns such that during a write operation, a write current pulse flows through each selected column. Another circuit supplies a compensation current pulse to the conductor rail that is determined by the selected column at the beginning of the write current pulse.

Inventors

• F. Tissaphirisi

Assignees

• 意法半导体国际公司

Dates

Publication Date

20260508

Application Date

20251110

Priority Date

20241108

Claims (14)

1. 1. A memory block, comprising: a plurality of phase change memory cells arranged in rows and columns; A first circuit, comprising: A first MOS transistor coupling a supply voltage to an input of the first circuit configured to receive a reference current, the first MOS transistor having a gate connected to the input; For each column, at least one second transistor coupling the supply voltage and a corresponding output of the first circuit coupled to the column, and A conductive rail connecting the input terminal to the gate of each second transistor; For each column, at least one third MOS transistor coupling the column to a corresponding output of the first circuit, and A second circuit configured to: Receiving a first signal indicating which columns to write during a write operation; Receiving a second control signal controlling the write operation, and Controlling each third MOS transistor based on the first signal and the second signal such that a write current pulse flows in each selected column during the write operation; A third circuit configured to: receiving a third signal indicating the number of selected columns and a fourth signal indicating the start of write current pulses in the selected columns for the write operation, and At the beginning of a write current pulse of the write operation, a pulse of compensation current determined by the third signal and the fourth signal is supplied to the conductive rail.
2. 2. The memory block of claim 1, wherein pulses of the compensation current determined based on the third and fourth signals compensate for voltage variations on the rail that result from each third MOS transistor of a selected column switching to an on state at a beginning of a write current pulse of the write operation.
3. 3. The memory block of claim 1, wherein, for each column, the at least one second MOS transistor coupling the supply voltage and a corresponding output of the first circuit is arranged in a current mirror configuration with the first MOS transistor.
4. 4. The memory block of claim 1, wherein the fourth signal determines a start of the compensation current pulse and the third signal determines a maximum value of the compensation current pulse.
5. 5. The memory block of claim 1, wherein the third signal comprises an indication of a maximum value of the write current pulse during the write operation.
6. 6. The memory block of claim 1, wherein the second signal indicates a beginning and an end of write current pulses flowing in a selected column.
7. 7. The memory block of claim 6, wherein the fourth signal is determined at least in part by the second signal.
8. 8. The memory block of claim 1, wherein the third circuit is further configured to receive a signal for selectively activating and deactivating supply of compensation current pulses to the conductive rail.
9. 9. The memory block of claim 1, wherein the third circuit comprises a single output connected to the conductive rail and configured to provide the compensation current pulse.
10. 10. The memory block of claim 9 wherein the third circuit comprises a plurality of parallel capacitors, each capacitor coupled to a first node through a first switch, and a second switch coupling the first node to an output of the third circuit, the third circuit configured to precharge the capacitors prior to the write operation, to close the second switch at the beginning of the compensation current pulse, and to close all or part of the first switch based on the third signal prior to closing the second switch.
11. 11. The memory block of claim 1, wherein: for each column, the third circuit includes a corresponding output connected to a gate of the at least one second MOS transistor coupled to the column; For each column, the third circuit includes a sub-circuit configured to supply a first current pulse starting with the compensation current pulse to an output of the third circuit corresponding to the column if the column is selected, and The compensation current pulses correspond to a set of first pulses.
12. 12. The memory block of claim 11, wherein: Each sub-circuit includes: a plurality of parallel capacitors, each capacitor coupled to the first node of the sub-circuit through a first switch, and A second switch coupling the first node of the sub-circuit to the output of the third circuit to which the sub-circuit is connected, and Each sub-circuit is configured to: Precharging the capacitor prior to the write operation; Closing a second switch of the sub-circuit at the beginning of the compensation current pulse if the corresponding column of the sub-circuit is selected, and All or a portion of the first switch is closed based on the third signal before closing the second switch.
13. 13. The memory block of claim 12, wherein, for each column, the subcircuit corresponding to the column is configured to receive a control signal from the at least one third switch corresponding to the column and to control its second switch to the on state based on the control signal.
14. 14. A memory, comprising: at least one memory block according to claim 1, and Circuitry configured to supply the reference current.

Description

Compensation current for PCM memory Priority claim The present application claims the priority benefit of french patent application No. fr2412227 filed at 11/8 of 2024, the entire contents of which are incorporated herein by reference to the maximum extent allowed by law. Technical Field The present disclosure relates generally to electronic circuits, and more particularly, to a Phase Change Memory (PCM) type memory that is a memory that includes at least one block (or in other words, at least one PCM memory block) that includes a plurality of PCM memory cells. Background A memory block of the Phase Change Memory (PCM) type comprises a plurality of memory cells arranged in a matrix of memory cells, i.e. in rows and columns of memory cells. Each PCM memory cell is configured to store an item of information, such as a bit, having a value determined by the resistance value of the memory cell. Thus, writing or programming a value in a memory cell means programming the state (e.g., crystalline or amorphous) of the phase change material in the memory cell such that the resistance value is programmed for the memory cell. Programming the state of the phase change material of the memory cell (and thus the state of the memory cell) is achieved by passing a current pulse through the memory cell, the shape of the pulse determining the state programmed in the memory cell. The current pulses are typically generated by a copy of a reference current, which is supplied, for example, by a digital-to-analog converter controlling the gate of the transistor. To speed up write operations in PCM memory blocks, it is desirable to be able to program memory cells belonging to each of the various columns simultaneously. However, this presents several problems. There is a need for a PCM memory block that allows simultaneous writing of multiple memory cells that each belong to a different column of the memory block. Some or all of the disadvantages of known PCM memory blocks need to be addressed. Disclosure of Invention One embodiment provides a PCM memory block comprising a plurality of phase change memory cells arranged in rows and columns, a first circuit comprising at least one first MOS transistor coupling a supply voltage to an input of a first circuit configured to receive a reference current and having a gate connected to the input, at least one second transistor coupling a supply voltage to a corresponding output of the first circuit coupled to the columns for each column, and a conductive rail connecting the input to a gate of the second transistor, at least one third MOS transistor coupling the columns to a corresponding output of the first circuit for each column, a second circuit configured to receive a first signal indicative of a column to be written during a write operation and to control a write operation, and to control a third MOS transistor based on the first signal and the second signal such that during a write operation, a write current pulse flows in each selected column, and a third circuit configured to receive a fourth signal indicative of a number of selected pulses and to determine a write current pulse at the start of the fourth signal and a fourth signal indicative of a write current pulse being supplied by the fourth rail. According to one embodiment, a compensation current pulse is determined based on the third signal and the fourth signal to compensate for a voltage change on the rail due to the third MOS transistor of the selected column switching to the on state at the beginning of the write current pulse. According to one embodiment, for each column, the at least one second MOS transistor coupling the supply voltage and the corresponding output of the first circuit is arranged in a current mirror configuration with the at least one first MOS transistor. According to one embodiment, the fourth signal determines the start of the compensation current pulse and the third signal determines the maximum value of the compensation current pulse. According to one embodiment, the third signal further comprises an indication of a maximum value of the write current pulse during the write operation. According to one embodiment, the second signal indicates the beginning and end of write current pulses flowing in the selected column. According to one embodiment, the fourth signal is at least partially determined by the second signal. According to one embodiment, the third circuit is further configured to receive a signal for selectively activating and deactivating the supply of compensation current pulses to the rail. According to one embodiment, the third circuit comprises a single output connected to the rail and configured to provide the compensation current pulse. According to one embodiment, the third circuit comprises a plurality of parallel capacitors, each capacitor being coupled to the first node through a first switch, and a second switch coupling the first node to an output of the third circuit, the third