CN-121999839-A - Memory, method for programming memory and memory system

Abstract

The embodiment of the disclosure provides a memory, a method for programming the memory and a memory system, wherein the memory comprises a memory cell array and peripheral circuits, and the memory cell array comprises memory cells. The peripheral circuit is configured to perform a first programming operation on the memory cells, programming the memory cells to an intermediate state, wherein the memory cells programmed to the intermediate state have an initial threshold voltage, and to perform a second programming operation on the plurality of memory cell groups, respectively, programming the initial threshold voltages of the memory cells to the threshold voltages, wherein the same memory cell group includes a plurality of memory cells having the same intermediate state.

Inventors

• ZHAO XIANGNAN
• LI CHENHUI
• Qian Yiyao
• LIU HONGTAO
• JIN LEI

Assignees

• 长江存储科技有限责任公司

Dates

Publication Date

20260508

Application Date

20241107

Claims (20)

1. 1. A memory, comprising: A memory cell array including memory cells, and Peripheral circuitry configured to: Performing a first programming operation on the memory cell, programming the memory cell to an intermediate state, wherein the memory cell programmed to the intermediate state has an initial threshold voltage, and And respectively executing a second programming operation on a plurality of memory cell groups to program the initial threshold voltage of the memory cells to a threshold voltage, wherein the same memory cell group comprises a plurality of memory cells with the same intermediate state.
2. 2. The memory of claim 1, wherein the peripheral circuitry is configured to: Performing a first programming of the second programming operation on the first memory cell group and the second memory cell group, respectively, by applying a first programming voltage and a second programming voltage to selected word lines connected to the plurality of memory cell groups, respectively, Wherein the initial threshold voltage of the memory cells of the first memory cell group is greater than the initial threshold voltage of the memory cells of the second memory cell group, and the first program voltage is greater than the second program voltage.
3. 3. The memory of claim 2, wherein the peripheral circuitry is further configured to: After the first programming is performed, verify operations are performed on the plurality of memory cell groups, respectively.
4. 4. The memory of claim 3, wherein an order in which the first programming is performed for each of the plurality of memory cells is the same as an order in which the verifying operation is performed for each of the plurality of memory cells.
5. 5. The memory of claim 3, wherein the peripheral circuitry is further configured to: And performing a second programming of the second programming operation on each of the plurality of memory cell groups in response to any one of the memory cell groups failing to pass the verify operation.
6. 6. The memory of claim 5, wherein the peripheral circuitry is configured to: Performing the second programming on the first memory cell group and the second memory cell group, respectively, by applying a third programming voltage and a fourth programming voltage to the selected word line, respectively, Wherein the third programming voltage is greater than the first programming voltage, and the fourth programming voltage is greater than the second programming voltage.
7. 7. The memory of claim 1, wherein the peripheral circuitry is configured to: after the second programming operation is performed on the first memory cell group, the second programming operation is performed on the second memory cell group, Wherein the initial threshold voltage of the memory cells of the first memory cell group is greater than the initial threshold voltage of the memory cells of the second memory cell group.
8. 8. The memory of claim 7, wherein the peripheral circuitry is configured to: Performing the second programming operation on the first memory cell group by sequentially applying a plurality of different first programming voltages to selected word lines connected to a plurality of the memory cell groups, and Performing the second programming operation on the second group of memory cells by applying a plurality of different second programming voltages to the selected word line, Wherein a voltage first applied to the selected word line among the plurality of first program voltages is greater than a voltage first applied to the selected word line among the plurality of second program voltages.
9. 9. The memory of claim 8, wherein the peripheral circuitry is further configured to: after the second program operation is performed on the first memory cell group, a first verify operation is performed on the first memory cell group.
10. 10. The memory of claim 9, wherein the peripheral circuitry is further configured to: And in response to the first memory cell group failing the first verify operation, performing the second program operation again on the first memory cell group.
11. 11. The memory of claim 10, wherein, among the plurality of different first programming voltages, a voltage applied to the selected word line at a previous time is smaller than a voltage applied to the selected word line at a subsequent time.
12. 12. The memory of claim 9, wherein the peripheral circuitry is further configured to: the second program operation is performed on the second memory cell group in response to the first memory cell group passing the first verify operation.
13. 13. The memory of any one of claims 1-12, wherein the peripheral circuitry is further configured to: When the second programming process is performed on any one of the memory cell groups, a program inhibit voltage is applied to a selected bit line connected to the other memory cell group.
14. 14. The memory of any one of claims 1-12, wherein a number of programmed states of the memory cells corresponding to the threshold voltage is greater than a number of the memory cell groups.
15. 15. The memory of any one of claims 1-12, wherein the number of memory cell groups is a natural number less than or equal to 5.
16. 16. The memory of any of claims 1-12, wherein the first programming operation and the second programming operation each comprise a step pulse programming operation.
17. 17. A memory system, comprising: the memory as in any one of claims 1-16, and And a controller in communication with the memory.
18. 18. A method of programming a memory, comprising: Performing a first programming operation on a memory cell of the memory, programming the memory cell to an intermediate state, wherein the memory cell programmed to the intermediate state has an initial threshold voltage, and And respectively executing a second programming operation on a plurality of memory cell groups to program the initial threshold voltage of the memory cells to a threshold voltage, wherein the same memory cell group comprises a plurality of memory cells with the same intermediate state.
19. 19. The method of claim 18, wherein performing the second programming operation on the plurality of memory cell groups, respectively, comprises: Performing a first programming of the second programming operation on the first memory cell group and the second memory cell group, respectively, by applying a first programming voltage and a second programming voltage to selected word lines connected to the plurality of memory cell groups, respectively, Wherein the initial threshold voltage of the memory cells of the first memory cell group is greater than the initial threshold voltage of the memory cells of the second memory cell group, and the first program voltage is greater than the second program voltage.
20. 20. The method of claim 19, wherein the method further comprises performing a verify operation on the plurality of memory cell groups, respectively, after performing the first programming.

Description

Memory, method for programming memory and memory system Technical Field The present disclosure relates to the field of semiconductor technology, and more particularly, to a memory, a method of programming a memory, and a memory system. Background The memory is a semiconductor device for digital data storage. The memory may include a nonvolatile memory that retains stored information even after power is turned off. By way of example, nonvolatile memory can include flash memory, read only memory, and the like. With the increase of storage capacity in a memory, reliability problems of data stored in the memory become one of research hotspots in the field of semiconductor technology. Disclosure of Invention Embodiments of the present disclosure provide a memory, a method of programming a memory, and a memory system that may at least partially solve the above-described problems or other problems in the art. An aspect of the present disclosure provides a memory including a memory cell array including memory cells and peripheral circuitry configured to perform a first programming operation on the memory cells, program the memory cells to an intermediate state, wherein the memory cells programmed to the intermediate state have an initial threshold voltage, and perform a second programming operation on a plurality of memory cell groups, respectively, program the initial threshold voltages of the memory cells to the threshold voltage, wherein a same memory cell group includes a plurality of memory cells having a same intermediate state. According to some embodiments of the present disclosure, the peripheral circuit is configured to perform first programming of a second programming operation on a first memory cell group and a second memory cell group, respectively, by applying a first programming voltage and a second programming voltage to selected word lines connected to the plurality of memory cell groups, respectively, wherein an initial threshold voltage of the memory cells of the first memory cell group is greater than an initial threshold voltage of the memory cells of the second memory cell group, and the first programming voltage is greater than the second programming voltage. According to some embodiments of the present disclosure, the peripheral circuit is further configured to perform a verify operation on the plurality of memory cell groups, respectively, after performing the first programming. According to some embodiments of the present disclosure, the order in which the first programming is performed on the plurality of memory cell groups, respectively, is the same as the order in which the verifying operation is performed on the plurality of memory cell groups, respectively. According to some embodiments of the present disclosure, the peripheral circuit is further configured to perform a second programming of the second programming operation on the plurality of memory cell groups, respectively, in response to any one of the memory cell groups failing the verify operation. According to some embodiments of the present disclosure, the peripheral circuit is configured to perform a second programming on the first memory cell group and the second memory cell group, respectively, by applying a third programming voltage and a fourth programming voltage, respectively, to the selected word line, wherein the third programming voltage is greater than the first programming voltage, and the fourth programming voltage is greater than the second programming voltage. According to some embodiments of the present disclosure, the peripheral circuitry is configured to perform a second programming operation on the second memory cell group after performing the second programming operation on the first memory cell group, wherein an initial threshold voltage of the memory cells of the first memory cell group is greater than an initial threshold voltage of the memory cells of the second memory cell group. According to some embodiments of the present disclosure, the peripheral circuit is configured to perform a second programming operation on a first memory cell group by sequentially applying a plurality of different first programming voltages to a selected word line connected to a plurality of memory cell groups, and to perform a second programming operation on a second memory cell group by applying a plurality of different second programming voltages to the selected word line, wherein a voltage first applied to the selected word line among the plurality of first programming voltages is greater than a voltage first applied to the selected word line among the plurality of second programming voltages. According to some embodiments of the present disclosure, the peripheral circuit is further configured to perform a first verify operation on the first memory cell group after performing the second program operation on the first memory cell group. According to some embodiments of the present disclosure, the peripheral circuit is furt