CN-121999840-A - Nonvolatile memory device performing write training

Abstract

A non-volatile memory device that performs write training is provided. The non-volatile memory device includes a plurality of memory dies connected to the controller through a first channel and configured to perform write training based on training data received from the controller. The plurality of memory dies includes a first memory die and a second memory die that each include a nonvolatile memory cell. The first memory die receives first training data from the controller in a first interval, compares the first training data with first pattern data in a second interval, and sends a first pass/fail value for the first training data to the controller. The second memory die receives second training data from the controller in a second interval.

Inventors

• CUI CHENGHE
• XUE CHANGGUI
• XUE MEILING
• Song Rouxi
• LI TAIMIN
• Cui Rongtun

Assignees

• 三星电子株式会社

Dates

Publication Date

20260508

Application Date

20250807

Priority Date

20241101

Claims (20)

1. 1. A non-volatile memory device, comprising: A plurality of memory dies connected to the controller through a first channel and configured to perform write training based on training data received from the controller, Wherein the plurality of memory dies includes a first memory die and a second memory die, the first memory die and the second memory die each including a nonvolatile memory unit, Wherein the first memory die is configured to receive first training data from the controller in a first interval and compare the first training data with first pattern data and send a first pass/fail value for the first training data to the controller in a second interval subsequent to the first interval, and Wherein the second memory die is configured to receive second training data from the controller in the second interval.
2. 2. The non-volatile memory device of claim 1, wherein the first memory die further comprises a first page buffer configured to store the first training data, and Wherein the second memory die further includes a second page buffer configured to store the second training data.
3. 3. The non-volatile memory device of claim 2, wherein the second memory die is configured to compare the second training data with second pattern data in a third interval subsequent to the second interval and send a second pass/fail value for the second training data to the controller.
4. 4. The non-volatile memory device of claim 2, wherein the first memory die is further configured to receive a first command and the first training data from the controller and store the first training data in the first page buffer in response to the first command.
5. 5. The non-volatile memory device of claim 2, wherein the first memory die is further configured to receive a second command from the controller and to compare the first training data with the first pattern data in response to the second command.
6. 6. The non-volatile memory device of claim 5, wherein the first memory die further comprises: a pattern generator configured to generate the first pattern data in response to the second command, and A comparator configured to compare the first training data received from the first page buffer with the first pattern data received from the pattern generator in response to the second command.
7. 7. The non-volatile memory device of claim 6, wherein the pattern generator comprises a linear feedback shift register.
8. 8. The non-volatile memory device of claim 1, wherein the first memory die is further configured to receive a third command from the controller and to send the first pass/fail value to the controller in response to the third command.
9. 9. The non-volatile memory device of claim 1, wherein the first training data corresponds to a first delay value and the second training data corresponds to the first delay value, and Wherein the first memory die is further configured to receive third training data from the controller corresponding to a second delay value different from the first delay value in a third interval subsequent to the second interval.
10. 10. The non-volatile memory device of claim 9, further comprising a data strobe pin configured to receive a data strobe signal from the controller, Wherein the first training data includes a training pattern having a delay corresponding to the first delay value relative to the data strobe signal, and Wherein the third training data includes a training pattern having a delay corresponding to the second delay value relative to the data strobe signal.
11. 11. The non-volatile memory device of claim 1, further comprising: A command/address pin configured to receive commands and addresses from the controller via command/address signal lines; a data pin configured to receive data from the controller via a data signal line, and A data strobe pin configured to receive a data strobe signal from the controller via a data strobe line, Wherein the first training data and the second training data are received via the data pin, an Wherein the first pass/fail value is sent over the command/address pin.
12. 12. The non-volatile memory device of claim 1, further comprising: A data pin configured to receive command, address and data from the controller via a data signal line, and A data strobe pin configured to receive a data strobe signal from the controller via a data strobe line, Wherein the first training data and the second training data are received via the data pin, an Wherein the first pass/fail value is sent over the data pin.
13. 13. A non-volatile memory device, comprising: A buffer chip connected to the controller through a first channel, and A plurality of memory dies connected to the buffer chip through a second channel and configured to perform a first write training between the controller and the buffer chip during a first write training interval, Wherein the plurality of memory dies includes: a first memory die configured to receive first training data corresponding to a first delay value from the controller through the buffer chip during a first interval of the first write training interval, and A second memory die configured to receive, during a second interval of the first write training interval, second training data corresponding to a second delay value different from the first delay value from the controller through the buffer chip, and Wherein the first memory die is configured to generate a first pass/fail value of the first training data during the second interval of the first write training interval and to send the first pass/fail value to the controller through the buffer chip.
14. 14. The non-volatile memory device of claim 13, wherein the second memory die is configured to generate a second pass/fail value for the second training data after the second interval of the first write training interval and to send the second pass/fail value to the controller through the buffer chip.
15. 15. The non-volatile memory device of claim 14, wherein the first memory die comprises: a first page buffer configured to store the first training data; A first pattern generator configured to generate first pattern data, and A first comparator configured to generate the first pass/fail value by comparing the first training data with the first pattern data, and Wherein the second memory die comprises: a second page buffer configured to store the second training data; A second pattern generator configured to generate second pattern data, and A second comparator configured to generate the second pass/fail value by comparing the second training data with the second pattern data.
16. 16. The non-volatile memory device of claim 13, wherein the plurality of memory dies are further configured to perform a second write training between the buffer chip and the plurality of memory dies during a second write training interval, Wherein the first memory die is further configured to receive third training data from the controller through the buffer chip during a first interval of the second write training interval, Wherein the first memory die is further configured to generate a third pass/fail value for the third training data during a second interval of the second write training interval, and the second memory die is configured to receive fourth training data from the controller through the buffer chip, and Wherein the first memory die is configured to receive fifth training data from the controller through the buffer chip during a third interval of the second write training interval, and the second memory die is further configured to generate a fourth pass/fail value for the fourth training data.
17. 17. The non-volatile memory device of claim 16, wherein the third training data and the fourth training data each correspond to a third delay value, and Wherein the fifth training data corresponds to a fourth delay value different from the third delay value.
18. 18. A non-volatile memory device, comprising: A plurality of memory dies connected to the controller through a first channel and configured to perform write training based on training data received from the controller, Wherein the plurality of memory dies includes: A first memory die including a first page buffer and configured to store first training data and reference training data received from the controller in the first page buffer and generate a first pass/fail value for the first training data based on a result of a logical operation of the reference training data and the first training data, and A second memory die including a second page buffer, and configured to store second training data and the reference training data received from the controller in the second page buffer, and generate a second pass/fail value for the second training data based on a result of a logical operation of the reference training data and the second training data, and Wherein when the first memory die generates the first pass/fail value, the second memory die is configured to receive the reference training data or the second training data.
19. 19. The non-volatile memory device of claim 18, wherein the first memory die is further configured to: During a first interval, receiving the reference training data and storing the reference training data in a first region of the first page buffer; During a second interval, dumping the reference training data stored in the first region of the first page buffer to a second region of the first page buffer; receiving the first training data and storing the first training data in the first region of the first page buffer during a third interval, and During a fourth interval, the first pass/fail value is generated by counting results of logical operations with respect to the reference training data and the first training data.
20. 20. The non-volatile memory device of claim 19, wherein the second memory die is further configured to: during the fourth interval, receiving the reference training data and storing the reference training data in a first region of the second page buffer; During a fifth interval, dumping the reference training data stored in the first region of the second page buffer to a second region of the second page buffer; Receiving the second training data and storing the second training data in the first region of the second page buffer during a sixth interval, and Generating the second pass/fail value by counting the result of the logical operation with respect to the reference training data and the second training data during a seventh section, and Wherein the first memory die is further configured to receive third training data during the seventh interval.

Description

Nonvolatile memory device performing write training Cross Reference to Related Applications Related application the present application claims priority from korean patent application No.10-2024-0153790 filed in the korean intellectual property office on 1/11/2024, the disclosure of which is incorporated herein by reference in its entirety. Technical Field One or more example embodiments of the present disclosure relate to memory devices, and more particularly, to a nonvolatile memory device that performs write training and a method for write training of a nonvolatile memory. Background The storage device may include a nonvolatile memory and a controller that controls the nonvolatile memory. Since the nonvolatile memory and the controller have different operation characteristics, initialization or training may be required during an initial operation of the storage device or an initial operation between the nonvolatile memory and the controller. In particular, a training operation may be performed to ensure reliability of data transmitted and received between the nonvolatile memory and the controller. Since data is transmitted and received between the nonvolatile memory and the controller based on training parameters obtained through a training operation, it may be important to obtain accurate training parameters. Disclosure of Invention One or more example embodiments of the present disclosure provide a nonvolatile memory device and a write training method of the nonvolatile memory device capable of reducing a write training operation time. According to an aspect of the present disclosure, there is provided a nonvolatile memory device including a plurality of memory dies (die) connected to a controller through a first channel and configured to perform write training based on training data received from the controller, wherein the plurality of memory dies include a first memory die and a second memory die, each including a nonvolatile memory unit, the first memory die configured to receive the first training data from the controller in a first interval and compare the first training data with first pattern data and transmit a first pass/fail value for the first training data to the controller in a second interval subsequent to the first interval, and the second memory die configured to receive the second training data from the controller in a second interval. According to another aspect of the present disclosure, there is provided a nonvolatile memory device including a buffer chip connected to a controller through a first channel, and a plurality of memory dies connected to the buffer chip through a second channel, and configured to perform a first write training between the controller and the buffer chip during a first write training interval, wherein the plurality of memory dies includes a first memory die configured to receive first training data corresponding to a first delay value from the controller through the buffer chip during a first interval of the first write training interval, and a second memory die configured to receive second training data corresponding to a second delay value different from the first delay value from the controller through the buffer chip during a second interval of the first write training interval, and generate a first pass/fail value of the first training data during the second interval of the first write training interval, and transmit the first pass/fail value to the controller through the buffer chip. According to another aspect of the present disclosure, there is provided a nonvolatile memory device including a plurality of memory dies connected to a controller through a first channel and configured to perform write training based on training data received from the controller, wherein the plurality of memory dies include a first memory die including a first page buffer and configured to store the first training data and the reference training data received from the controller in the first page buffer and generate a first pass/fail value with respect to the first training data based on a result of a logical operation of the reference training data and the first training data, and a second memory die including a second page buffer and configured to store the second training data and the reference training data received from the controller in the second page buffer and generate a second pass/fail value with respect to the second training data based on a result of a logical operation of the reference training data and the second training data, and receive the second training data or the second training data when the first memory die generates the first pass/fail value. According to another aspect of the present disclosure, there is provided a nonvolatile memory device including a plurality of memory dies connected to a controller through a first channel, wherein the plurality of memory dies includes a first memory die including a first page buffer and configured to receiv